Abstract: The present invention relates to a slow down circuit for use with a digital computer having a microprocessor ready line, an address bus and a data bus. The slow down circuit is comprised of an address decode logic unit for producing an inhibit signal when predetermined bit patterns appear on the address bus. The predetermined bit patterns represent special computer functions which require the computer to operate at normal speed. A slow down signal generator is connected to the address bus and the data bus for generating a bi-level signal. A combiner is connected to the address decode logic unit and the slow down signal generator for combining the inhibit signal and the bi-level signal to produce a control signal. The control signal has a first and a second logic level. When the control signal is at the first logic level the computer operates at normal speed.