Patents Assigned to Candescent Intellectual Property Services, Inc.
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Patent number: 6727048Abstract: A method for photo-imageable lacquer deposition for a display device. In one embodiment, a layer of photo-imageable lacquer is deposited on top of a faceplate of a display device. Portions of the lacquer layer are removed and selected portions of the lacquer layer remain deposited in the sub-pixel areas of the faceplate.Type: GrantFiled: December 20, 2001Date of Patent: April 27, 2004Assignees: Candescent Intellectual Property Services, Inc., Candescent Technologies CorporationInventors: Olof M. Trollsas, Theodore S. Fahlen
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Patent number: 6722935Abstract: In a flat-panel display structure having a spacer with laterally segmented face electrodes, one embodiment of the present invention defines the length of the laterally segmented face electrode sections to minimize zero current shift variation in electron trajectories. Advantageously, the present embodiment of the invention prevents image quality degradation. In one embodiment, values for variation in the uniformity of and dicing tolerance are combined to calculate a design optimum for the length of laterally segmented face electrodes. Zero current shift variation from fluctuations in wall resistance falls off with the length of laterally segmented face electrodes. Zero current shift due to first order angular alignment during dicing varies linearly with the dashed electrode length. In one embodiment of the present invention, an optimal value is calculated by combining these effects to minimize zero current shift. Advantageously, in one embodiment, the electrode segments are individually testable.Type: GrantFiled: June 29, 2001Date of Patent: April 20, 2004Assignee: Candescent Intellectual Property Services, Inc.Inventors: James C. Dunphy, Christopher J. Spindt
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Patent number: 6722937Abstract: A flat-panel display is hermetically sealed by a process in which a first plate structure (30) is positioned generally opposite a second plate structure (32) such that sealing material (34) provided over the second plate structure lies between the plate structures. In a gravitational sealing technique, the first plate structure is positioned vertically below the second plate structure. The sealing material is heated so that it moves vertically downward under gravitational influence to meet the first plate structure and seal the plate structures together. In a global-heating gap-jumping technique, the plate structures and sealing material are globally heated to cause the sealing material to jump a gap between the sealing material and the first plate structure. When the first plate structure is positioned vertically above the second plate structure, the sealing material moves vertically upward to meet the first plate structure and close the gap.Type: GrantFiled: July 31, 2000Date of Patent: April 20, 2004Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc., Sony CorporationInventors: Paul N. Ludwig, Theodore S. Fahlen, Shinji Kanagawa, Jennifer Y. Sun
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Patent number: 6714017Abstract: A method and system for detecting electrical short circuit defects in a plate structure of a flat panel display, for example, a field emission display (FED) is disclosed. In one embodiment, the process first applies a stimulation to the electrical conductors of the plate structure. Next, the process creates an infra-red thermal mapping of a cathode region of the FED. For example, an infra-red array may be used to snap a picture of the cathode of the FED. Then, the process analyzes the infra-red thermal mapping to determine a region of the FED which contains the electrical short circuit defect. Another embodiment localizes the defect to one sub-pixel by performing an infra-red mapping of the region which the previous IR mapping process determined to contain the electrical short circuit defect. Then, the process analyzes this infra-red mapping to determine a sub-pixel of the FED which contains the electrical short circuit defect.Type: GrantFiled: November 30, 2000Date of Patent: March 30, 2004Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: Marius Enachescu, Sergey Belikov, Stephen F. Meier
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Patent number: 6710525Abstract: An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.Type: GrantFiled: October 19, 1999Date of Patent: March 23, 2004Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: Jueng Gil Lee, Christopher J. Spindt, Johan Knall, Matthew A. Bonn, Kishore K. Chakravorty
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Patent number: 6691404Abstract: A flat-panel display is fabricated according to a process in which a liquid-containing film (92, 116, 124, 132, 144, or 166) is formed over a substrate (80). In addition to suitable liquid, the liquid-containing film contains oxide or/and hydroxide. Liquid is removed from the liquid-containing film to convert it into a solid porous film (82 or 150) having (a) a porosity of at least 10% along an exposed face of the film, (b) an average resistivity of 108-1014 ohm-cm at 25° C., and (c) an average thickness of no more than 20 &mgr;m. A spacer (24) formed with at least a segment of the substrate and overlying solid porous film is positioned between opposing first and second plate structures (20 and 22) of the display. The second plate structure (22) emits light upon receiving electrons emitted by the first plate structure (20).Type: GrantFiled: January 25, 2001Date of Patent: February 17, 2004Assignees: Candescent Intellectual Property Services, Inc., Candescent Technologies Corporation, NanoPore Inc.Inventors: Roger W. Barton, Michael J. Nystrom, Bob L. Mackey, Lawrence S. Pan, Shiyou Pei, Stephen Wallace, Douglas M. Smith
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Patent number: 6676470Abstract: An embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment provides a method of fabricating a cathode in which the passivation layer and the metallic gate chromium are masked and patterned simultaneously. The method effectuates patterning of the passivation layer as necessary and simultaneously fixes a location for both access spots and inter-pixel electrical isolation areas to chromium constituting the metallic gate. Importantly, the present implementation effectively eliminates a conventionally requisite subsequent metallic gate chromium masking and etching step. Advantageously, this effectively streamlines and economizes cathode fabrication. The present embodiment thus reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. This effectively reduces the unit cost of flat panel CRTs.Type: GrantFiled: September 28, 2001Date of Patent: January 13, 2004Assignees: Candescent Intellectual Property Services, Inc., Candescent Technologies Corporation, Sony CorporationInventors: Jueng-Gil Lee, Hidenori Kemmotsu
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Patent number: 6677705Abstract: One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a direct via masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required direct via masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.Type: GrantFiled: September 28, 2001Date of Patent: January 13, 2004Assignees: Candescent Intellectual Property Services Inc., Sony Corporation, Sony Electronics Inc.Inventors: Jueng-Gil Lee, Kazuo Kikuchi, Matthew A. Bonn
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Patent number: 6632117Abstract: A method for attaching a faceplate and a backplate of a field emission display device. Specifically, one embodiment of the present invention discloses a method for protecting a silicon nitride passivation layer from reacting with a glass frit sealing material that contains lead oxide during an oven sealing or laser sealing process. The passivation layer protects row and column electrodes in the display device. A barrier material fully encapsulates the silicon nitride passivation layer. In one embodiment, silicon dioxide is the barrier material. In another embodiment, spin-on-glass is the barrier material. In still another embodiment, cermet is the barrier material.Type: GrantFiled: August 3, 2001Date of Patent: October 14, 2003Assignees: Candescent Intellectual Property Services, Inc., Candescent Technologies CorporationInventors: Jueng-Gil Lee, Theodore S. Fahlen
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Patent number: 6630786Abstract: A light-emitting device (42, 68, 80, 90, or 100) suitable for a flat-panel CRT display contains a plate (54), a light-emissive region (56), a light-blocking region (58), and a light-reflective layer (60 or 70). The light-emitting device achieves one or more of the following characteristics by suitably implementing the light-reflective layer or/and providing one or more layers (72, 82, 92, and 100) along the light-reflective layer: (a) reduced electron energy loss as electrons pass through the light-reflective layer, (b) gettering along the light-reflective layer, (c) reduced secondary electron emission along the light-reflective layer, (d) reduced electron backscattering along the light-reflective layer, and (e) reduced chemical reactivity along the light-reflective layer.Type: GrantFiled: March 30, 2001Date of Patent: October 7, 2003Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: William J. Cummings, Lawrence S. Pan, Christopher J. Spindt, George B. Hopple, Colin D. Stanners, James C. Dunphy, Shiyou Pei, Theodore S. Fahlen
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Patent number: 6624592Abstract: A method of removing contaminant particles from faceplates in newly fabricated field emission displays so that a uniform distribution of contaminants is achieved at the emitter sites of the display. During the initial operation of a field emission dislay device contaminants are removed from the display faceplate by electron induced desorption. The emission current profile at the emitter sites is selected so that the distribution of readsorbed contaminants is equalized. The variations in current emission compensate for shadowing effects due to spacer walls to produce a uniform readsorption distribution. The emitter sites may driven using an animated contrast image at a constant current for the display.Type: GrantFiled: December 18, 2001Date of Patent: September 23, 2003Assignees: Candescent Intellectual Property Services, Inc, Candescent Technologies CorporationInventors: James C. Dunphy, Donald J. Elloway
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Patent number: 6617772Abstract: A flat-panel display contains a pair of plate structure (20 and 22) separated by a spacer (24) having a rough face (54 or 56). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as depressions (60, 62, 64, 66, 70, 74, or 80) or/and protuberances (82, 84, 88, and 92). Various techniques are presented for manufacturing the display, including the rough-faced spacer.Type: GrantFiled: December 11, 1998Date of Patent: September 9, 2003Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc., Advanced Technology Materials, IncInventors: Roger W. Barton, Kollengode S. Narayanan, Bob L. Mackey, John M. Macaulay, George B. Hopple, Donald R. Schropp, Jr., Michael J. Nystrom, Sudhakar Gopalakrishnan, Shiyou Pei, Xueping Xu
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Patent number: 6571464Abstract: Methods and structures are provided which support spacer walls in a position which facilitates installation of the spacer walls between a faceplate structure and a backplate structure of a flat panel display. In one embodiment, spacer feet are formed at opposing ends of the spacer wall. These spacer feet can be formed of materials such as ceramic, glass and/or glass frit. The spacer feet support the corresponding spacer wall on the faceplate (or backplate) structure. Tacking electrodes can be provided on the faceplate (or backplate) structure to assert an electrostatic force on the spacer feet, thereby holding the spacer feet in place during installation of the spacer wall. The spacer wall can be mechanically and/or thermally expanded prior to attaching both ends of the spacer wall to the faceplate (or backplate) structure. The spacer wall is then allowed to contract, thereby introducing tension into the spacer wall which tends to straighten any inherent waviness in the spacer wall.Type: GrantFiled: April 26, 2001Date of Patent: June 3, 2003Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: Theodore S. Fahlen, Alfred S. Conte, Robert M. Duboc, Jr., George B. Hopple, John K. O'Reilly, Vasil M. Chakarov, Robert L. Marion, Steve T. Cho, Robert G. Neimeyer, Jennifer Y. Sun, David L. Morris, Christopher J. Spindt, Kollengode S. Narayanan
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Publication number: 20030062823Abstract: A flat-panel cathode-ray tube display contains electron-emissive regions (54) spaced non-uniformly apart from one another in a line of the electron-emissive regions so as to better utilize the space where the electron-emissive regions are located. Alternatively or additionally, electron focusing can be appropriately made more concentrated by implementing each electron-emissive region as two or more portions 54A-54F) situated suitably with respect to openings (86A-86F) in an electron-focusing system (76).Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Applicant: Candescent Technologies Corporation and Candescent Intellectual Property Services, Inc.Inventor: James C. Dunphy
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Patent number: 6528930Abstract: A conductive focus waffle structure for focusing electrons emitted from a cathode portion of a flat panel display device. In one embodiment, the conductive focus waffle structure comprises a grid of material comprised of substantially orthogonally oriented rows and columns. The substantially orthogonally oriented rows and columns define openings therebetween having sufficient size to allow electrons emitted from a cathode portion of a flat panel display device to pass therethrough. The focus waffle grid further comprises a lower dielectric portion adapted to be coupled to the cathode portion of the flat panel display device and an upper conductive portion coupled to the lower dielectric portion, the upper conductive portion adapted to focus the electrons passing through the openings.Type: GrantFiled: September 12, 2000Date of Patent: March 4, 2003Assignee: Candescent Intellectual Property Services, Inc.Inventors: David C. Chang, Arthur J. Learn, Bob L. Mackey, Paul M. Drumm, David L. Morris
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Patent number: 6500885Abstract: A liquid chemical formulation suitable for making a thin solid polycarbonate film contains polycarbonate material and a liquid typically capable of dissolving the polycarbonate material to a concentration of at least 1%. The polycarbonate material may consist of homopolycarbonate or/and copolycarbonate. Examples of the liquid include pyridine, a ring-substituted pyridine derivative, pyrrole, a ring-substituted pyrrole derivative, pyrrolidine, a pyrrolidine derativive, chlorobenzene, and cyclohexanone. A liquid film (36A) of the formulation is formed over a substructure (30) and processed to remove the liquid. The resultant solid polycarbonate film can later serve as a track layer through which charged particles (70) are passed to form charged-particle tracks (72). Apertures (74) are created through the track layer by a process that entails etching along the tracks. The aperture-containing polycarbonate track layer is typically used in fabricating a gated electron-emitting device.Type: GrantFiled: October 29, 1999Date of Patent: December 31, 2002Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: John D. Porter, Michael P. Skinner, Stephanie Simmons
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Patent number: 6489718Abstract: A spacer (140) suitable for use in a flat panel display is formed with ceramic, transition metal, and oxygen. At least part of the oxygen is bonded to the transition metal or/and constituents of the ceramic to form a uniform electrically resistive material having a resistivity of 105-1010 ohm-cm and a secondary electron emission coefficient of less than 2 at 2 kilovolts.Type: GrantFiled: July 18, 2000Date of Patent: December 3, 2002Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: Anthony P. Schmid, Christopher J. Spindt, David L. Morris, Theodore S. Fahlen, Yu Nan Sun
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Patent number: 6448708Abstract: A flat panel display and a method for forming a flat panel display. In one embodiment, the flat panel display includes a cathodic structure which is formed within an active area on a backplate. The cathodic structure includes a emitter electrode metal composed of strips of aluminum overlain by a layer of cladding material. The use of aluminum and cladding material to form emitter electrode metal gives emitter electrode metal segments which are highly conductive due to the high conductivity of aluminum. By using a suitable cladding material and processing steps, a bond between the aluminum and the cladding material is formed which has good electrical conductivity. In one embodiment, tantalum is used as a cladding material. Tantalum forms a bond with the overlying resistive layer which has good electrical conductivity. Thus, the resulting structure has very high electrical conductivity through the aluminum layer and high conductivity into the resistive layer.Type: GrantFiled: May 31, 2000Date of Patent: September 10, 2002Assignee: Candescent Intellectual Property Services, Inc.Inventors: Kishore K. Chakravorty, Swayambu Ramani, Stephanie J. Oberg, Johan Knall, Duane A. Haven, Ronald S. Besser, Paul J. Louris, Arthur J. Learn, Christopher J. Spindt, Roger W. Barton
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Patent number: 6448948Abstract: A device for and method of eliminating undesirable vertical segments of uneven brightness in flat panel field emission display (FED) screens. Within the FED screen, a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Amplitude modulated signals are provided to the columns by column drivers and discrepancies in settling times among the column drivers cause vertical segments of uneven brightness on the display screen. The present invention normalizes settling time of the column amplifier that can be variant due to differences in semiconductor processing and manufacturing. The present invention includes specialized circuitry coupled to the column drivers for sensing an output of the column driver and determining a difference between the output and a threshold at a particular time before the output has completely settled to a target voltage.Type: GrantFiled: January 25, 2000Date of Patent: September 10, 2002Assignee: Candescent Intellectual Property Services, Inc.Inventor: Jay Friedman
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Patent number: 6433473Abstract: A structure and method for forming an column electrode for a field emission display device wherein the column electrode is disposed beneath the field emitters and the row electrode. In one embodiment, the present invention comprises depositing a resistor layer over portions of a column electrode. Next, an inter-metal dielectric layer is deposited over the column electrode. In the present embodiment, the inter-metal dielectric layer is deposited over portions of the resistor layer and over pad areas of the column electrode. After the deposition of the inter-metal dielectric layer, the column electrode is subjected to an anodization process such that exposed regions of the column electrode are anodized. In so doing, the present invention provides a column electrode structure which is resistant to column to row electrode shorts and which is protected from subsequent processing steps.Type: GrantFiled: February 25, 1999Date of Patent: August 13, 2002Assignee: Candescent Intellectual Property Services, Inc.Inventors: Kishore K. Chakravorty, Fariborz Nadi, Christopher J. Spindt, Ronald L. Hansen, Colin D. Stanners