Abstract: The present disclosure provides an LDMOS device and a preparation method thereof, including: providing a substrate including a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first blocking structure, where the first gate structure is formed above a portion of the body region and a portion of the first drift region, the body region and the first drift region respectively include first and second regions not covered by the first gate structure, and the first blocking structure is formed above the second region; performing an ion implantation process, where a part of ions are implanted into the first region of the body region to form a body region contact region, and a part of ions are implanted into the second region after passing through the first blocking structure to form a first doped region.

Abstract: Disclosed is an electro-static discharge device based on a PNPN structure. First intersection boundary is formed between first P-well and N-well; second intersection boundary is formed between N-well and second P-well; first ion injection region is arranged on surface region of first P-well; second ion injection region is arranged on surface region of second P-well; first N-ion boundary injection region is arranged at position of first intersection boundary formed by the intersection of surface region of first P-well and surface region of N-well; second N-ion boundary injection region is arranged at position of second intersection boundary formed by intersection of surface region of N-well and surface region of second P-well; and parasitic discharge circuit spans first P-well, N-well, and second P-well, and parasitic discharge circuits is connected to first ion injection region and second ion injection region respectively.

Abstract: The present invention provides a wafer cleaning method and a method for manufacturing semiconductor device. The wafer cleaning method includes: protonating a cleaning solution with a protonator; cleaning a wafer surface with the protonated cleaning solution so that the cleaned wafer surface carries an amount of negative charge smaller than an amount of negative charge present on a wafer surface that has been cleaned with a non-protonated cleaning solution and is covered with a liquid film of the cleaning solution; and purging the wafer surface with a drying gas to remove the liquid film from a center of the wafer surface towards its periphery. The technique proposed in the present invention is able to desirably suppress static electricity on a wafer surface and effectively reduce device failure that may be caused by static electricity, thereby increasing overall yield of integrated circuit manufacture.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device include: a substrate having a STI structure; a first polysilicon structure layer, an isolation dielectric layer, and a second polysilicon structure layer sequentially stacked on the STI structure. The first polysilicon structure layer is undoped polysilicon. The second polysilicon structure layer is heavily boron-doped polysilicon. Contact hole structures are provided on the first polysilicon structure layer for monitoring a target doping concentration of boron during high-concentration boron ion implantation and annealing activation of the second polysilicon structure layer. A fabrication method for the semiconductor device is also provided.

Abstract: A semiconductor device structure and a method of forming the structure are disclosed. The semiconductor device structure includes a first capacitor and a second capacitor. The first capacitor is formed in a first redundant area, and the second capacitor is formed in a second redundant area. Since the first and second capacitors are formed in the respective redundant areas of the substrate, they will not unnecessarily occupy portions of a device area.

Abstract: The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

Abstract: The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device include: a substrate having a STI structure; a first polysilicon structure layer, an isolation dielectric layer, and a second polysilicon structure layer sequentially stacked on the STI structure. The first polysilicon structure layer is undoped polysilicon. The second polysilicon structure layer is heavily boron-doped polysilicon. Contact hole structures are provided on the first polysilicon structure layer for monitoring a target doping concentration of boron during high-concentration boron ion implantation and annealing activation of the second polysilicon structure layer. A fabrication method for the semiconductor device is also provided.

Abstract: Disclosed are a metal-insulator-metal (MIM) capacitor structure and a method for fabricating the structure. The MIM capacitor structure includes: a substrate; a capacitor structure comprising a bottom metal layer, an interlayer dielectric layer and a top metal layer sequentially stacked over the substrate; an opening extending downward through the top metal layer into the interlayer dielectric layer; a recess located at a side wall of the opening, and extending from a bottom of the opening downward into the interlayer dielectric layer; and a sidewall spacer located in the opening, which extends over a side wall of the top metal layer and downward into the recess so as to fill it up, wherein the interlayer dielectric layer is made of the same material as the sidewall spacer. The MIM capacitor structure and a fabricating method therefor can improve the breakdown voltage of the MIM capacitor structure.

Abstract: An electrical leakage test structure and an electrical leakage testing method are disclosed. The electrical leakage test structure comprises: a substrate; a first well region and a second well region, which are both formed in the substrate; a first shallow trench isolation structure formed between the second and first well regions; a first source/drain region formed in the first well region; a plurality of second source/drain regions formed in the second well region; and a test gate formed on the substrate. In the electrical leakage testing method, a plurality of electrical leakage test structures with different designed dimensions are tested to perform leakage current evaluation on each electrical leakage test structure, and a designed dimension vs.