Patents Assigned to CAPITAL MICROELECTRONICS CO., LTD.
  • Patent number: 10181716
    Abstract: A hot-swap protection circuit includes: a hot-swap circuit, a hot-swap detection circuit, and an N-well generation circuit, where the hot-swap detection circuit is configured to detect whether hot-swap is performed on the hot-swap circuit, and feed back a detection result to the N-well generation circuit; and the N-well generation circuit is configured to receive the detection result fed back by the hot-swap detection circuit, and output a control signal according to the detection result, to protect the hot-swap circuit. The hot-swap detection circuit is used to detect whether hot-swap is performed on the hot-swap circuit, and the detection result is fed back to the N-well generation circuit, so that the N-well generation circuit outputs a control signal according to the detection result fed back by the hot-swap detection circuit, to protect the hot-swap circuit, thereby preventing the hot-swap of the hot-swap circuit from burning a host or a peripheral device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: January 15, 2019
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Qinghua Xue
  • Patent number: 10037072
    Abstract: The present invention relates to a chip power supply method and a chip, where configuration memory array provides configuration voltage to an NMOS transmission gate, and an LDO circuit supplies power to the chip. The method includes: determining that a working state of the chip switches from a first state to a second state, where the first state and the second state are separately an initial mode, a program mode or a user mode; and adjusting, according to the working state of the chip, a configuration bit to adjust an output voltage of the LDO circuit. The present invention reduces power dissipation of the chip during memory configuration, and improves working performance thereof during the user mode.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: July 31, 2018
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Xueping Zhou, Zixian Chen, Qinghua Xue
  • Patent number: 9979398
    Abstract: A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 22, 2018
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng Mai
  • Patent number: 9754644
    Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 5, 2017
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Yuanpeng Wang, Ping Fan, Jia Geng
  • Patent number: 9727415
    Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: August 8, 2017
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Jia Geng, Yuanpeng Wang, Ping Fan
  • Publication number: 20170168549
    Abstract: The present invention relates to a chip power supply method and a chip, where configuration memory array provides configuration voltage to an NMOS transmission gate, and an LDO circuit supplies power to the chip. The method includes: determining that a working state of the chip switches from a first state to a second state, where the first state and the second state are separately an initial mode, a program mode or a user mode; and adjusting, according to the working state of the chip, a configuration bit to adjust an output voltage of the LDO circuit. The present invention reduces power dissipation of the chip during memory configuration, and improves working performance thereof during the user mode.
    Type: Application
    Filed: June 15, 2015
    Publication date: June 15, 2017
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Xueping ZHOU, Zixian CHEN, Qinghua XUE
  • Publication number: 20160364290
    Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.
    Type: Application
    Filed: November 27, 2014
    Publication date: December 15, 2016
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Jia GENG, Yuanpeng WANG, Ping FAN
  • Publication number: 20160344391
    Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.
    Type: Application
    Filed: December 11, 2014
    Publication date: November 24, 2016
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Ping FAN, Jia GENG, Yuanpeng WANG
  • Publication number: 20160320451
    Abstract: A simulation verification method for Field Programmable Gate Array (FPGA) function modules and a system thereof. The method includes: generating all test cases by enumerating all parameter characteristics of FPGA function modules; generating, according to an input type and input parameter characteristics of an FPGA function module under test, a simulation test bench matching configuration of the corresponding FPGA function module under test; and randomly generating, by the simulation test bench, a test stimulus and a corresponding expected output according to the input parameter characteristics of the FPGA function module under test, comparing the expected output with an actual output obtained after the test stimulus is applied to the test case corresponding to the FPGA function module under test, and outputting a test report of the FPGA function module under test according to a comparison result.
    Type: Application
    Filed: December 30, 2014
    Publication date: November 3, 2016
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Yuanpeng WANG, Ping FAN, Jia GENG
  • Publication number: 20160322084
    Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.
    Type: Application
    Filed: December 30, 2014
    Publication date: November 3, 2016
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Yuanpeng WANG, Ping FAN, Jia GENG
  • Publication number: 20160315619
    Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.
    Type: Application
    Filed: December 11, 2014
    Publication date: October 27, 2016
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Ping FAN, Jia GENG, Yuanpeng WANG
  • Publication number: 20160315620
    Abstract: An extensible and configurable logic element, wherein the logic element includes: multiple logic parcels, each logic parcel includes two logic cells; each logic cell includes seven inputs, three outputs, an addition carry input, an addition carry output, a six-input and two-output look-up table, a one bit full adder, a first register, and a second register; wherein, the first register stores a signal output by the first output of the look-up table or a carry signal of the full adder according to the configuration; the second register stores a signal output by the second output of the look-up table or an output signal of the full adder according to the configuration; the addition carry output in the current logic cell is connected to the addition carry input in the higher logic cell of the current logic cell, including an addition carry chain in the logic element.
    Type: Application
    Filed: December 11, 2014
    Publication date: October 27, 2016
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventors: Ping FAN, Jia GENG, Yuanpeng WANG
  • Patent number: 9287871
    Abstract: Embodiments of the present invention disclose a level up shifter circuit. The level up shifter circuit further includes two field effect transistors connected in series and a control circuit. Sources of the two field effect transistors and a source of a sixth field effect transistor are respectively connected to a drain of a first field effect transistor and a drain of a second field effect transistor of the conversion circuit, and the control circuit is turned on when a first voltage signal and a third voltage signal are zero at the same time and is turned off in other situations. The level up shifter circuit according to the embodiments of the present invention can effectively solve the problem that an output state is unknown.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: March 15, 2016
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng Mai
  • Patent number: 9172327
    Abstract: A crystal oscillator circuit includes: a crystal resonator circuit, generating an oscillation signal; an inverting amplification circuit, whose amplifier input end is coupled to receive the oscillation signal, in which an inverting amplifier outputs an inverting amplified output signal; a bias circuit, having a bias circuit input end and a bias circuit output end, in which the bias circuit output end generates a bias circuit output signal controlled by the bias circuit input end, and the bias circuit output signal is coupled to a second control end of the inverting amplification circuit; and a peak detection circuit, comparing the inverting amplified output signal with a reference signal, regulating a peak detector output signal, and feeding the peak detector output signal into the bias circuit input end.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 27, 2015
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng Mai
  • Patent number: 9106236
    Abstract: A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: August 11, 2015
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng Mai
  • Publication number: 20150130529
    Abstract: Embodiments of the present invention disclose a level up shifter circuit. The level up shifter circuit further includes two field effect transistors connected in series and a control circuit. Sources of the two field effect transistors and a source of a sixth field effect transistor are respectively connected to a drain of a first field effect transistor and a drain of a second field effect transistor of the conversion circuit, and the control circuit is turned on when a first voltage signal and a third voltage signal are zero at the same time and is turned off in other situations. The level up shifter circuit according to the embodiments of the present invention can effectively solve the problem that an output state is unknown.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 14, 2015
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng MAI
  • Publication number: 20150061786
    Abstract: A crystal oscillator circuit includes: a crystal resonator circuit, generating an oscillation signal; an inverting amplification circuit, whose first amplifier input end is coupled to receive the oscillation signal, in which an inverting amplifier outputs an inverting amplified output signal; a bias circuit, having a bias circuit input end and a bias circuit output end, in which the bias circuit output end generates a bias circuit output signal controlled by the bias circuit input end, and the bias circuit output signal is coupled to a second amplifier input end; and a peak detection circuit, comparing the inverting amplified output signal with a reference signal, regulating a peak detector output signal, and feeding the peak detector output signal into the bias circuit input end, in which the bias circuit includes a self-adjusting circuit, for isolating a power supply from a second input end of the inverting amplifier.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 5, 2015
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng MAI
  • Publication number: 20150061736
    Abstract: A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 5, 2015
    Applicant: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng MAI