Abstract: A computing device implements a functional programming in hardware and operates as a reduction processor. Programs to be evaluated are represented as a directional graph of closures, where each part of a program is represented by a closure. During execution, this directional graph of closures is gradually reduced according to the reduction rules of the declarative language used. The device has an active associative object storage having storage cells able to store and execute at least part of a computer program. The device has several ports that contain storage cells and which are able to exchange and compare data and programs through a unification of internal and external behaviors.

Abstract: A reduction processor controlled by a program having a structure reduces the structure in a number of reduction steps implementing different kinds of reduction operations. A first order processor of this kind includes an active storage (1, 2) which in turn includes a number of active storage cells, each able to store information which could give rise to a reduction. A communication net communicates the result of each reduction to all cells having connection to the result. The processor includes a control unit in common for all the storage cells. Preferably, at least one of the storage cells, called core cell or structure arithmetic unit, is able to perform all kinds of reductions, and the rest of the cells, called object storage cells, are able to perform only limited number of reductions. Further, several reduction processors could be connected to each other by a network and thereby form a higher order reduction processor.

Abstract: The invention relates to a package for VLSI-chips. A substrate means (A1;B1;C1), a frame means (3;14) and a lid means (A5;B5;C5) makes a housing having an inside cavity. First connection means (4;16) are provided on the inside of said cavity in electrical contact with external contact means (6;22) on the outside of the housing. A chip (A3;B3;C3) having second connection means (8;B19) is placed inside the cavity. At least one interconnection film (A2;B2;C2) is placed adjacent the chip (A3;B3;C3) and has third and fourth connection means (9,5;21,20). The third connection means (9;21) are positioned to make contact with the second connection means (8;B19) on the chip. The fourth connection means (5;20) are positioned to make contact with the first connection means (4;16) inside the cavity. Individual ohmic contacts are provided individually between chosen among the third and fourth connection means (9, 5;21,20) for making connection between chosen of the first and second connection means (4,8;16,22).

Abstract: A method and an arithmetic unit for structural arithmetic processing is described. Data words are stored in several registers, each data word having a mark part and an information part. The mark part includes a mark indicating if the register in question being in use or not. The data words are arranged in lists. Each of the lists is stored in a predetermined number of the registers. The mark part of each of the words in the lists stored in the registers is marked in use indicating that one of the lists has at least a part stored in the actual register. The list having a part stored in said actual register includes a list instruction denoting which kind of list it is and the relation between the lists is apparent from the arrangement of the lists in the registers.

Abstract: A low-voltage DC power supply, e.g. 5 V output, is fed from a higher-voltage input DC source, e.g. 300 V. A plurality of switched transformers each comprise a primary winding (L1) for switchably connecting to the input, a secondary winding (L2) for switchably connecting to the output, electronic switches (M1-M8) for alternatingly switching the windings (L1, L2) in opposite polarities, and common control means (10) for performing the switching such that in the plurality of transformers, no two thereof are simultaneously switching. For removing the influence of rapid output current surges, a filter (L9, L10, C10-C12) is arranged on the input side.

Abstract: An associative memory is provided having a first control bus arrangement (any type, Vr, cpb, set.s, match, r/w.s, r/w.b, r/w.r, Wand.a, Wand.b, Wor, s.a, reset.b, mode.a mode.a*, prech, ba, mode.b, grant.b, prio etc) for external control and a second memory bus arrangement (t1, t2, id, anv, v0, v1, v2, v3) for data. The memory includes several storage cells (1) for storing a composed information. Each storage cell stores at least one mark, which indicates at least select state(s) or non select state(s) for said storage cell. The mark(s) are set by search operations among said cells. A priority decoder (2) is provided to which all said storage cells are coupled and which selects one out of several of said storage cells. At least one global bus (4, 5) is provided for making logical operations of the type AND and OR between said storage cells. A closure head (11) is provided in each storage cell for communicating with said buses and to control said storage cell to take part in an actual logical operation.

Abstract: A method and an electronic communication link for piece of information serial transmission includes at multiple conductor constellation having at least three conductors (R, S, T). There could be provided at least three different combinations ((H,L,L), (L,H,L), (L,L,H)) of signal levels (V.sub.L, V.sub.H) on the conductors, which combinations are set in a prescribed order. One kind of piece of information, for instance "0", is transmitted by a change of combination in said prescribed order. The other kind of piece of information, for instance "1" is transmitted by a change of combination backwards against the prescribed order.

Abstract: A method and a device to perform arithmetic, arithmetical, logical and related operations on numerical value elements is characterized by providing an input list including the numerical value elements to be processes, and instruction information on a predetermined number of inputs/output buses. The operation on the numerical value elements on the input list is directly controlled and performed using the instruction information. Various computing circuits adapted to perform a specific operation on the numerical value representations are connected on the input buses, thereby providing the results of their computations in parallel. The calculation in the arithmetic logical unit is performed by rewriting the elements in the input list. The result is presented as an output list.

Abstract: A fast memory bit cell suitable for implementation in VLSI techniques permitting a high cell density. The cell includes a cell circuit in which a logical bit value is storable, a first connection permanently tied to a supply voltage, a second, third and fourth connection, each able to assume a different control state. Each combination of control states on the second, third and fourth connection sets the memory bit cell in an individual among a set of functional states.