Abstract: A negative voltage decoder applies a negative voltage to the sense line of a selected row of a memory array but not to sense lines of unselected rows. The negative voltage decoder includes a negative voltage source, an array of P-channel transistors, and a negative voltage address signal generator. P-channel transistors in the array have gates coupled to address lines, so that address signals on the address lines turn on the P-channel transistors and connect only the selected sense line to the negative voltage source. A negative voltage charge pumps in the negative voltage address signal generator generates address signals lower than the negative voltage source. In one embodiment, the transistor array has rows of P-channel transistors which fit the pitch of the memory array and individual P-channel transistors which are stacked laterally away from the memory array, and each row of P-channel transistors couples through a set of individual transistor to a set of sense lines.

Abstract: A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer to a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation.

Abstract: Word line stress is used to narrow the distribution of threshold voltages after an erase of an array of memory cells. One embodiment of the invention provides a method for erasing an array including a standard erase technique followed by extra erase pulses to create a margin between threshold voltages of the cells and the erase verify level, then applying word line stress to narrow the distribution of threshold voltages. Another embodiment in addition includes verifying that all of the memory cells are still erased after applying word line stress and if any of the memory cells were over-stressed and are not erased, repeating the method but using less word line stress. The erase methods according to embodiments of the present invention can be implemented by an external CPU which executes an erase program or by circuitry embedded in an EEPROM.