Patents Assigned to CATLAM, LLC
  • Patent number: 10573610
    Abstract: Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 25, 2020
    Assignee: CATLAM, LLC
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Publication number: 20190320530
    Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
    Type: Application
    Filed: May 28, 2019
    Publication date: October 17, 2019
    Applicant: CATLAM, LLC
    Inventors: Kenneth S. BAHL, Konstantine KARAVAKIS
  • Patent number: 10349520
    Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 9, 2019
    Assignee: CATLAM, LLC
    Inventors: Konstantine Karavakis, Kenneth S. Bahl