Patents Assigned to Cavium International
  • Patent number: 11010318
    Abstract: Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: May 18, 2021
    Assignee: CAVIUM INTERNATIONAL
    Inventors: Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid
  • Patent number: 10749800
    Abstract: Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 18, 2020
    Assignee: Cavium International
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Harish Krishnamoorthy
  • Patent number: 10713089
    Abstract: Method and system embodying the method for load balancing of scheduled jobs among a plurality of engines encompassing determining a number of cluster credits for each of a plurality of clusters that comprise at least one engine capable of processing a scheduled job; determining a number of engine credits for each of the plurality of engines comprising each of the at least one engine in accordance with a number of jobs assigned to each of the plurality of engines; evaluating the determined number of cluster credits and the determined number of engine credits in accordance with a credit evaluation policy; and assigning the job to one of the plurality of engines in accordance with the evaluation, is disclosed.
    Type: Grant
    Filed: May 20, 2017
    Date of Patent: July 14, 2020
    Assignee: CAVIUM INTERNATIONAL
    Inventors: Timothy Toshio Nakada, Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid, Mark Jon Kwong
  • Patent number: 10700998
    Abstract: A network switch capable of supporting cut-though switching and interface channelization with enhanced system performance. The network switch includes a plurality of ingress tiles, each tile including a virtual output queue (VOQ) scheduler operable to submit schedule requests to a fabric scheduler. Data is requested in unit of quantum which may aggregate multiple packets, which reduces schedule latency. Each request is associated with a start-of-quantum (SoR) state or a middle-of-quantum (MoR) state to support cut-through. The fabric scheduler performs a multi-stage scheduling process to progressively narrow the selection of requests, including stages of arbitration in virtual output port level, virtual output port group level, tile level, egress port level and port group level. Each tile receives the grants for its requests and accordingly sends request data to a switch fabric for transmission to the destination egress ports.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 30, 2020
    Assignee: Cavium International
    Inventor: Weihuang Wang
  • Patent number: 10680957
    Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: June 9, 2020
    Assignee: Cavium International
    Inventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 10656992
    Abstract: An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: May 19, 2020
    Assignee: Cavium International
    Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Hutchison