Abstract: A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.

Abstract: A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.

Abstract: A resistively folded single stage differential amplifier capable of accommodating a low input common mode without impacting the performance of a bias current source, while also providing a high input impedance to allow for the use of the linear termination resistors. The differential amplifier provides an amplified output signal with a common mode referenced to an upper bound of an input power supply. The differential amplifier includes an input sub-stage and a transistor sub-stage resistively folding the input sub-stage.

Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

Abstract: In an embodiment, authenticated hardware and authenticated software are cryptographically binded using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. This cryptographic binding technique is referred to herein as secure software and hardware association (SSHA).

Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).

Abstract: An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc of a current node represents a character match in an expression of a character associated with the current node. Arcs which are not valid may be pruned. Non-valid arcs may include arcs which point back to a designated node(s), or arcs that point to the same next node as the designated node(s) for the same character. Typically, the majority of arcs associated with a node are non-valid. Therefore, pruning the non-valid arcs may greatly reduce graph storage requirements.

Abstract: In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.

Abstract: An apparatus, and corresponding method, for performing a search for a match of at least one expression in an input stream is presented. A graph including a number of interconnected nodes is generated. A compiler may assign at least one starting node and at least one ending node. The starting node includes a location table with node position information of an ending node and a sub-string value associated with the ending node. Using the node position information and a string comparison function, intermediate nodes located between the starting and ending nodes may be bypassed. The node bypassing may reduce the number of memory accesses required to read the graph.

Abstract: A security subsystem is provided with at least a first security engine, a first set of registers and a control portion to perform a first security operation for each of a first number of data blocks of each of a first number of data segments of a first data object. In one embodiment, the security subsystem is provided with two security engines and two sets of registers to respectively perform the first security operation and a second security operation for the first data object and a similarly constituted second data object. In one embodiment, the first and second security operations are DES and hashing operations. In one embodiment, the multi-method security subsystem is embodied in a multi-service system-on-chip.

Abstract: A method and apparatus for transparent processing of IPsec network traffic by a security processor in line between a framer and a network processor. Security processor parses packet header and tail information to determine if encryption or decryption is required. After encryption or decryption is completed packet header and tail information is modified to reflect the changes in the packet such as length of the packet. The modified packet is then passed on to the network processor or framer.

Abstract: A security processing apparatus is described comprising: a cryptographic processor having a first plurality of security processing resources initially allocated to process a first type of data traffic and a second plurality of security processing resources initially allocated to process a second type of data traffic; a monitor module to monitor load on the first plurality of security processing resources and the second plurality of security processing resources as the first and second types of data traffic are processed; a resource allocation module to reallocate some of the first plurality of security processing resources from the first type of data traffic to the second type of data traffic if detected load on the second plurality of security processing resources is above a specified threshold value.

Abstract: In one embodiment, an apparatus comprises a microcontroller unit to store instructions into an execution queue. The apparatus also comprises an execution queue unit to generate a widely decoded functional execution instruction based on at least one instruction stored in the execution queue. Additionally, the apparatus comprises a functional unit to execute the widely decoded functional execution instruction asynchronous to the generation of the widely decoded functional execution instruction.

Abstract: In one embodiment, a computer-implemented method comprises receiving a data cipher operation. The method also comprises processing the data cipher operation. The processing of the operation includes generating a number of portions of ciphertext from plaintext, wherein a load operation associated with the generating of at least one portion of the ciphertext executes prior to a store operation associated with the generating of a prior portion of the ciphertext.

Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Abstract: A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory.

Abstract: A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align the transition points.

Abstract: An apparatus is described comprising: a set of logic blocks configured to perform designated data processing functions; a set of redundant logic blocks also configured to perform the designated data processing functions; and a logic block selector module to replace one or more of the set of logic blocks with one or more of the set of redundant logic blocks according to specified logic block replacement conditions.

Abstract: A method and apparatus to encipher a block of data using the data encryption standard comprising exclusive-oring, using an exclusive-or gate, the output from a merged permutation and expansion (MPE) and a sub key block, and sending the output from the exclusive-or gate to a selection function.

Abstract: A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.