Patents Assigned to Celerity Research, Inc.
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Patent number: 7170306Abstract: One embodiment of the present invention is a method for fabricating a structure useful for testing circuits that includes steps of: (a) aligning a first side of a connector-holder comprised of electrical connectors having retractable ends that are extendable out of the first side of the connector-holder and having retractable ends that are extendable out of a second side of the connector-holder with a substrate; and (b) connecting ends extendable out of the first side to pads on the substrate to form the structure.Type: GrantFiled: March 12, 2003Date of Patent: January 30, 2007Assignee: Celerity Research, Inc.Inventors: Konstantine N. Karavakis, Tom T. Nguyen
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Patent number: 6998864Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a flexible substrate having contactors on a first side and pads on a second side; (b) a rigid substrate having vias aligned with the pads on the second side of the flexible substrate; (c) an adhesive layer comprised of a compliant adhesive material having vias aligned with the pads on the second side of the flexible substrate; the adhesive layer being affixed to the flexible substrate and the rigid substrate; (d) a card; (e) electrical connectors that are retained in the vias of the rigid substrate and the adhesive layer, which electrical connectors have first and second retractable ends, wherein the first retractable ends contact pads on the substrate, and the second retractable ends contact pads on the card; and (f) a clamp that is adapted to fit over the substrate and the adhesive layer, the clamp having an opening to provide access to the contactors, wherein the clamp is connected to the card.Type: GrantFiled: June 28, 2005Date of Patent: February 14, 2006Assignee: Celerity Research, Inc.Inventors: Konstantine N. Karavakis, Tom T. Nguyen
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Patent number: 6984996Abstract: A probing system or process for electrical testing of a device fabricated on a wafer also conditions terminals such as solder balls on the device to improve uniformity of the heights of the terminals and improve the reliability of connections to an interconnect substrate in a flip-chip package or to a printed circuit board in a chip-on-board application. The system can employ a probe card that is a printed circuit board and/or is substantially identical to interconnect substrates used in flip-chip packaging. The probe card can be replaceable on a test head to allow for quick changes the reduce ATE downtime and to accommodate device changes such as a die shrink. Probe tips on the probe card can be the contact pads or bumps that are the normal electrical contact structures of the interconnect substrates.Type: GrantFiled: May 1, 2003Date of Patent: January 10, 2006Assignee: Celerity Research, Inc.Inventors: Mark L. DiOrio, Robert M. Hilton
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Patent number: 6975127Abstract: The planarity of external terminals or a ball grid array on a device package can be improved through use of test probes that flatten the electrical terminals while forming the electrical contacts for package testing. After testing, the package has external terminals with improved planarity that improves the electrical connections formed during assembly of a system containing the package.Type: GrantFiled: November 19, 2003Date of Patent: December 13, 2005Assignee: Celerity Research, Inc.Inventor: Mark L. DiOrio
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Patent number: 6946859Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a substrate having contactors on a first side and pads on a second side; (b) a card having pads on a first side; and (c) interconnectors that electrically connect the pads on the second side of the substrate with the pads on the card; wherein at least one of the interconnectors includes at least a portion that does not melt at temperatures in a range from about 183° C. to about 230° C., and the distance between the substrate and the card is determined by a dimension of the at least a portion.Type: GrantFiled: April 16, 2003Date of Patent: September 20, 2005Assignee: Celerity Research, Inc.Inventors: Konstantine N. Karavakis, Tom T. Nguyen
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Patent number: 6924654Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a flexible substrate having contactors on a first side and pads on a second side; (b) a rigid substrate having vias aligned with the pads on the second side of the flexible substrate; (c) an adhesive layer comprised of a compliant adhesive material having vias aligned with the pads on the second side of the flexible substrate; the adhesive layer being affixed to the flexible substrate and the rigid substrate; (d) a card; (e) electrical connectors that are retained in the vias of the rigid substrate and the adhesive layer, which electrical connectors have first and second retractable ends, wherein the first retractable ends contact pads on the substrate, and the second retractable ends contact pads on the card; and (f) a clamp that is adapted to fit over the substrate and the adhesive layer, the clamp having an opening to provide access to the contactors, wherein the clamp is connected to the card.Type: GrantFiled: April 16, 2003Date of Patent: August 2, 2005Assignee: Celerity Research, Inc.Inventors: Konstantine N. Karavakis, Tom T. Nguyen