Abstract: The invention discloses a neural tissue stimulator, characterized in that the neural tissue stimulator comprises a multiple of microneedles and a chip comprising at least one comparator with adaptive level, sequence control circuit, at least one capacitor stack built by n capacitors and 2n switches, at least one buffer capacitor outside the at least one capacitor stack, at least two additional switches outside the at least one capacitor stack, a CMOS-Logic, wherein further, the neural tissue stimulator comprises an interposer layer comprising holes for the multiple of microneedles and a lid. The neural tissue stimulator is characterized in, that the chip is located on one surface of the interposer layer and that the lid and the interposer layer form a capsule for the chip. Further, the neural tissue stimulator is adapted to be electrically self-sufficient.

Abstract: The invention discloses a cardiac pacemaker, characterized in that the cardiac pacemaker comprises a multiple of microneedles and a chip comprising at least one comparator with adaptive level, sequence control circuit, at least one capacitor stack built by n capacitors and 2n switches, at least one buffer capacitor outside the at least one capacitor stack, at least two additional switches outside the at least one capacitor stack, a CMOS-Logic, wherein further, the cardiac pacemaker comprises an interposer layer comprising holes for the multiple of microneedles and a lid. The cardiac pacemaker is characterized in that the chip, is located on one surface of the interposer layer and that the lid and the interposer layer form a capsule for the chip. Further, each microneedle of the array of microneedles has a distal end which protrudes from the chip and the cardiac pacemaker is adapted to be electrically self-sufficient.

Abstract: The invention discloses a device for collection of tiny charges in the Nano-Coulomb-range and below, comprising at least one capacitor stack build by n capacitors and 2n switches (n?N), at least one further capacitor outside the capacitor stack as buffer capacity, at least two additional switches and a DC input source. The n capacitors are dedicated to be sequentially charged by the DC input source one after the other, wherein the 2n switches in the capacitor stack couple the n capacitors sequentially to the DC input source. The at least one further capacitor is dedicated to be charged from the n capacitors of the capacitor stack at once.