Patents Assigned to Cennoid Technologies, Inc.
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Patent number: 6404356Abstract: A method and apparatus are provided for compressing data. The method includes the steps of determining a flux, scaling factor and sign of a difference between a new sample and a previous sample and encoding the difference of the new sample over the previous sample based upon the determined flux, scaling factor and sign of the new sample.Type: GrantFiled: May 22, 2000Date of Patent: June 11, 2002Assignee: Cennoid Technologies, Inc.Inventor: Spyros Panaoussis
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Patent number: 5949355Abstract: The present invention relates to data compression systems and methods wherein text can be compressed by encoding repetitions of blocks of characters, or through a straight encoding scheme that converts eight-bit character values to four-bit character values by eliminating values for characters that are not valid word-starting characters or valid next-letter characters for a given preceding letter. Block compression is accomplished through the use of data structures that track the successive occurrence of valid block-repetition starting characters, and their lengths. Repeat-relative block compression is accomplished by detecting character sequences that can be expressed as the value of a previously-occurring character sequence plus or minus an offset.Type: GrantFiled: August 21, 1997Date of Patent: September 7, 1999Assignee: Cennoid Technologies, Inc.Inventor: Spyros Panaoussis
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Patent number: 5896100Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.Type: GrantFiled: January 13, 1997Date of Patent: April 20, 1999Assignee: Cennoid Technologies, Inc.Inventor: Spyros Panaoussis
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Patent number: 5684478Abstract: The present invention relates to data compression systems and methods wherein text can be compressed by encoding repetitions of blocks of characters, or through a straight encoding scheme that converts eight-bit character values to four-bit character values by eliminating values for characters that are not valid word-starting characters or valid next-letter characters for a given preceding letter. Block compression is accomplished through the use of data structures that track the successive occurrence of valid block-repetition starting characters, and their lengths. Repeat-relative block compression is accomplished by detecting character sequences that can be expressed as the value of a previously-occurring character sequence plus or minus an offset.Type: GrantFiled: December 6, 1994Date of Patent: November 4, 1997Assignee: Cennoid Technologies, Inc.Inventor: Spyros Panaoussis
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Patent number: 5594438Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.Type: GrantFiled: September 30, 1994Date of Patent: January 14, 1997Assignee: Cennoid Technologies Inc.Inventor: Spyros Panaoussis