Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system memory coupled to the microprocessor. The microprocessor also includes a cache memory, comprising an array of storage elements for storing cache lines, indexed by an index input. One of the storage elements of the array indexed by an index portion of an address of the prefetched cache line stored in the prefetch buffer is storing a replacement candidate line for the prefetched cache line. The microprocessor also includes control logic that determines whether the replacement candidate line in the cache memory is invalid, and if so, replaces the replacement candidate line in the one of the storage elements with the prefetched cache line from the prefetch buffer.

Abstract: A filtering apparatus in a hardware random number generator that prevents the random number generator (RNG) from outputting a contiguous string of zeros or ones longer than a specified length. The maximum length is programmable in the apparatus. The apparatus includes a counter that keeps a current count of contiguous zero bits in a series of bytes generated by the RNG. An adder generates a sum of the current zero bit count and the number of leading zeros in the next byte generated. If the sum exceeds the maximum length, then the filter throws out the byte rather than accumulating it. Otherwise, if the byte contains all zeros, the counter is updated with the sum; or if the byte contains trailing zeros, the counter is updated with the number of trailing zeros; otherwise the counter is cleared. The apparatus does the same for contiguous one bits.