Patents Assigned to Centellax, Inc.
  • Patent number: 8456238
    Abstract: A traveling wave amplifier includes a tapered attenuator network for mitigating the effects of DC bias inductor self-resonance. The amplifier includes a gain stages connected in a ladder network for successively amplifying a forward traveling wave caused by an input signal to produce an output signal. A back termination is coupled to the gain stages to absorb backwards traveling waves created by reflections from the gain stages and an output of the amplifier. An inductive DC bias circuit is coupled to the gain stages near the back termination for providing DC bias to the gain stages. A tapered multi-section frequency selective attenuator network is connected between the DC bias circuit and a first one of the gain stages for reducing the effect of self-resonance of the inductive DC bias circuit on the output signal.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 4, 2013
    Assignee: Centellax, Inc.
    Inventors: Jeffrey W. Meyer, Jerry Orr
  • Patent number: 6788148
    Abstract: A termination network simultaneously provides a voltage-limited output direct current (dc) bias and termination of a broadband distributed amplifier operating down to an arbitrary low frequency. It is capable of being fabricated in a single Integrated Circuit (IC) chip, without the excess power dissipation associated with biasing through a termination resistor, and without the use of external inductor networks. It also limits the maximum dynamic voltage swing on the outputs of the active gain devices used within the distributed amplifier, so as to increase the reliability of the distributed amplifier under large signal over drive conditions.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 7, 2004
    Assignee: Centellax, Inc.
    Inventors: Jerry Orr, Sean Pham, Jeffrey W. Meyer
  • Patent number: 6759907
    Abstract: A distributed and adjustable level-shifting network is integrated with cascaded amplifiers, eliminating the need for a direct current (dc) blocking capacitor between the amplifiers. The level-shifting network can be adjusted to compensate for process variations and to balance the crossover frequency response of the cascaded amplifiers.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: July 6, 2004
    Assignee: Centellax, Inc.
    Inventors: Jerry Orr, Tim Bagwell
  • Patent number: 6680991
    Abstract: A lock detector is described for detecting a difference between the frequencies of a first and a second input signal. The lock detector includes first and second beat generators configured to generate corresponding beat signals based on the first and second input signals. The second beat signal is phase shifted relative to the first beat signal. A chatter elimination module combines the two chattery beat signals to produce a third corresponding beat signal that is substantially free of chatter. Using this clean beat signal and either of the input signals, a lock detection module produces a lock detection signal, which indicates whether the difference between the frequencies of the first and second input signals is within a prescribed tolerance.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: January 20, 2004
    Assignee: Centellax, Inc.
    Inventor: Germán Gutierrez