Patents Assigned to CENTIPEDE SEMI LTD.
  • Patent number: 10452400
    Abstract: A processor includes a pipeline and a multi-bank Branch-Target Buffer (BTB). The pipeline is configured to process program instructions including branch instructions. The multi-bank BTB includes a plurality of BTB banks and is configured to store learned Target Addresses (TAs) of one or more of the branch instructions in the plurality of the BTB banks, to receive from the pipeline simultaneous requests to retrieve respective TAs, and to respond to the requests using the plurality of the BTB banks in the same clock cycle.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 22, 2019
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Avishai Tvila, Alberto Mandler
  • Patent number: 10296346
    Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions in a first segment of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions in a second segment of the instructions, at least partially in parallel with processing of the instructions of the first segment by the first hardware thread, in accordance with a specification of register access that is indicative of data dependencies between the first and second segments.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 21, 2019
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Alberto Mandler, Shay Koren, Jonathan Friedmann
  • Patent number: 10296350
    Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 21, 2019
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Alberto Mandler, Shay Koren, Jonathan Friedmann
  • Patent number: 10185561
    Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served from an internal memory in the processor, based on the identified relationship.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: January 22, 2019
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Jonathan Friedmann
  • Patent number: 10180841
    Abstract: A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a memory, along with multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions. A monitoring unit monitors the instructions in the processing pipeline and records respective monitoring tables indicating the registers accessed in processing the instructions in different sequences of the instructions, and parallelizes among the hardware threads of the processor, using the respective monitoring tables, execution of repetitions of at least first sequences of the instructions.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: January 15, 2019
    Assignee: Centipede Semi Ltd.
    Inventors: Noam Mizrahi, Alberto Mandler, Shay Koren, Jonathan Friedmann
  • Patent number: 10013255
    Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 3, 2018
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Jonathan Friedmann, Ido Goren, Shay Koren, Noam Mizrahi, Alberto Mandler
  • Patent number: 9858075
    Abstract: A method includes, in a processor that processes multiple segments of a sequence of instructions of program code, wherein each segment is defined as either speculative or non-speculative, dispatching the instructions of the segments into at least one instruction buffer. The instructions of the segments are executed, and, in each segment, at least some of the executed instructions of the segment are speculatively-committed from the at least one instruction buffer independently of any other segment. Dispatching the instructions includes dispatching the instructions of a first segment into a first region of the at least one instruction buffer, and dispatching the instructions of a second segment, which occurs later in the program code than the first segment, into a second region of the at least one instruction buffer before all the instructions of the first segment have been dispatched into the first region.
    Type: Grant
    Filed: December 6, 2015
    Date of Patent: January 2, 2018
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Omri Tennenhaus, Noam Mizrahi, Alberto Mandler
  • Patent number: 9715390
    Abstract: A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.
    Type: Grant
    Filed: April 19, 2015
    Date of Patent: July 25, 2017
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Alberto Mandler, Shay Koren, Jonathan Friedmann
  • Patent number: 9575897
    Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 21, 2017
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Jonathan Friedmann
  • Patent number: 9430244
    Abstract: A method includes processing a sequence of instructions of program code that are specified using one or more architectural registers, by a hardware-implemented pipeline that renames the architectural registers in the instructions so as to produce operations specified using one or more physical registers. At least first and second segments of the sequence of instructions are selected, wherein the second segment occurs later in the sequence than the first segment. One or more of the architectural registers in the instructions of the second segment are renamed, before completing renaming the architectural registers in the instructions of the first segment, by pre-allocating one or more of the physical registers to one or more of the architectural registers.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 30, 2016
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Omri Tennenhaus, Alberto Mandler, Noam Mizrahi
  • Patent number: 9348595
    Abstract: A method includes, in a processor that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 24, 2016
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Alberto Mandler, Shay Koren, Jonathan Friedmann
  • Patent number: 9208066
    Abstract: A method includes, in a processor that executes instructions of program code, identifying a region of the code containing one or more segments of the instructions that are at least partially repetitive. The instructions in the region are monitored, and an approximate specification of register access by the monitored instructions is constructed for the region. Execution of the segments in the region is parallelized using the specification.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: December 8, 2015
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Alberto Mandler, Shay Koren, Jonathan Friedmann
  • Patent number: 9135015
    Abstract: A method includes, in a processor that executes instructions of program code, monitoring the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions. In response to detecting a branch mis-prediction in the monitored instructions, the specification is corrected so as to compensate for the branch mis-prediction. Execution of the repetitive sequence is parallelized based on the corrected specification.
    Type: Grant
    Filed: December 25, 2014
    Date of Patent: September 15, 2015
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Alberto Mandler, Shay Koren, Jonathan Friedmann