Abstract: An interpolating D/A converter architecture includes a reference voltage generator, a decoding switch network, a routing switch, and an interpolating buffer. The reference voltage generator generates a plurality of reference voltages. The decoding switch network is coupled to the reference voltage generator for selecting two reference voltages from the plurality of reference voltages in response to the plurality of high bits of digital video signals. The routing switch is coupled to the decoding switch network for selectively providing a first reference voltage and a second reference voltage in response to a plurality of low bits of the digital video signals. And the interpolating buffer is coupled to the routing switch for outputting an interpolated analog signal in response to the first reference voltage and the second reference voltage. Eventually, the present invention can save half the D/A reference lines and half the associated decoding switch rows, and thereby save the die cost.

Abstract: The present invention discloses a single-ended sense amplifier including an output circuit having an output terminal for indicating a state of a bitline node. In addition, a noise margin circuit; and an n-channel transistor are provided for coupling or decoupling an input terminal of the output circuit with the bitline node. The variable logic-threshold inverter has a larger logic threshold voltage in response to a lower voltage level of a precharge signal and a smaller logic-threshold voltage in response to a higher voltage level of the precharge signal. The difference between the two logic-threshold voltages represents the possible noise margin. Furthermore, a power down control circuit is provided to be coupled to the bitline node for reducing the static power consumption of the single-ended sense amplifier. The single-ended sense amplifier according to the present invention provides a higher and adjustable noise margin and occupies a smaller area on a semiconductor wafer.