Abstract: Some embodiments include a method for detecting and interrupting a cache-based side-channel attack. The method includes: (1) at least calibrating one or more chiplets of a network by calculating a threshold; (2) determining one or more device heartbeat vectors of the one or more chiplets, the one or more device heartbeat vectors being derived at least part from one or more measurements of activity of one of more dedicated security processors associated with the one or more chiplets; (3) determining that a particular chiplet of the one or more chiplets is being attacked with a cache-based side-channel attack, the determining being based at least in part on a computed disparity exceeding the threshold; and (4) employing countermeasures against the cache-based side-channel attack of the particular chiplet, the countermeasures including revoking one or more access rights of the particular chiplet on the network.

Abstract: A cryptographic method includes at least (1) receiving a message for encryption, (2) encrypting the message to obtain message ciphertext, the encryption including at least one or more operations that include at least one or more XOR operations, (3) computing a tag on a concatenation that includes at least a nonce, the message ciphertext, and other data, (4) encrypting the tag to obtain one or more ordered blocks of tag ciphertext, the encryption including at least one or more operations that include at least one or more XOR operations, (5) appending the one or more ordered blocks of tag ciphertext to the message ciphertext to obtain final ciphertext, and (6) transmitting the final ciphertext to a second chiplet.

Abstract: A computational system with a primary processor and a secondary processor executing executable code, the secondary processor executing at least one clock cycle behind the primary processor. The primary processor comprising (i) two primary delay buffers, including a final primary delay buffer, and (ii) a primary historical storage buffers operably linked to the final primary delay buffer. The secondary processor including a secondary delay buffer and a secondary historical storage buffer operably liked with the secondary delay buffer. The system including a circuit for performing a comparison between first data values from the final primary delay buffer and second data values from the secondary delay buffer. The system configured, if the first data values and the second data values do not match, for storing the first data values in the primary historical storage buffer and the second data values in the secondary historical storage buffer.

Abstract: An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3×3×64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.

Abstract: A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values, and a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. The X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

Abstract: A computer-implemented method includes training at least a generative adversarial network, the method operable on one or more processors. The method includes at least (1) applying pattern extraction to a set of training data to extract one or more feature embeddings representing one or more features of the training data, (2) attenuating the one or more feature embeddings to create one or more attenuated feature embeddings, (3) providing the one or more attenuated embeddings to a generator of the generative adversarial network as a condition to at least partly control the generator in generating synthetic data, the providing being performed automatically and dynamically during training of the generator, and (4) with the generator, generating synthetic data based at least in part on the attenuated embeddings.

Abstract: A first chiplet parses at least a message into ordered message blocks that are associated with index values. The first chiplet generates a substitution value by executing a pseudo-random number generator using a seed value that is computed with at least (i) a first random or pseudo-random number and at least (ii) a first message block. The first chiplet generates a sequencing value by executing a pseudo-random number generator using a seed value that is computed with at least (i) a second random or pseudo-random number and at least (ii) an index value for the first message block. The first chiplet generates a first ciphertext block with at least the substitution value and the sequencing value and further generates a second ciphertext block at least partly with the first ciphertext block. The blocks are concatenated and transmitted to a second chiplet.

Abstract: A system and method for a memory device is disclosed. A substrate is provided. A first ferromagnetic layer is disposed over the substrate. A spacer layer is disposed over the first ferromagnetic layer. A second ferromagnetic layer is disposed over the spacer layer and magnetized in a first direction. A first charge current pulse is passed through the substrate, along a direction perpendicular to the first direction and orients the magnetization of the first ferromagnetic layer in a second direction perpendicular to the first direction. A second charge current pulse is passed through the substrate to selectively switch the magnetization of the first ferromagnetic layer either in the first direction or a direction opposite to the first direction based on a direction of the second charge current. The direction of switched orientation of the magnetization of the first ferromagnetic layer indicates a first value or a second value.

Abstract: A system and method for a device is disclosed. A first logic device and a second logic device are provided. Each of the first logic device and the second logic device include at least three inputs and one output, wherein, the output is based on majority of the inputs. The output of the first logic device is selectively fed to the second logic device, wherein, the first logic device and the second logic device together form an adder circuit.

Abstract: A computing system includes (1) a primary processor executing executable instructions and generating first instruction data associated with the executable instructions, (2) a secondary processor executing the executable instructions one or more clock cycles behind the primary processor and generating secondary instruction data associated with the executable instructions, (3) a first first-in first-out (FIFO) buffer for the primary processor, (4) a second FIFO buffer for the secondary processor, (5) circuitry storing at least some of the first instruction data in the first FIFO buffer and at least some of the second instruction data in the second FIFO buffer, (6) compare circuitry comparing a first portion of first instruction data and a second portion of second instruction data that are associated with a given clock cycle, and (7) control circuitry halting the primary and secondary processors responsive to a mismatch between the first portion and the second portion.

Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.

Abstract: A system and method for a logic device is disclosed. Three synthetic antiferromagnet (SAF) nanotracks are disposed over a substrate along a first axis. A connector nanotrack connects the three input nanotrack about a second end of the nanotracks. An output nanotrack is disposed about a central portion of the connector nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to selectively move nucleated skyrmion to the output nanotrack, with presence of Skyrmion indicating an output value of the first value.

Abstract: A system and method for a logic device is disclosed. A plurality of synthetic antoferromagnet (SAF) nanotracks including a first input nanotrack, a second input nanotrack and an output nanotrack are disposed over a substrate along a first axis. Output nanotrack is disposed between the input nanotracks. Each nanotrack have a first end and a second end. A SAF connector nanotrack connects the first input nanotrack, the second input nanotrack, and the output nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to move nucleated skyrmion to the second end of the output nanotrack. Skyrmion at the output indicates an output value of the first value.

Abstract: A system and method for a logic device is disclosed. A plurality of substrates are provided. At least one input nanomagnet is disposed over each of the plurality of substrates. The plurality of input nanomagnets are disposed substantially equidistant from each other. The plurality of input nanomagnets are each a single domain nanomagnet. A spacer layer is disposed over the plurality of input nanomagnets. An output magnet is disposed over the spacer layer.

Abstract: A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates: an integer form fraction at a first bitwidth and a second bitwidth greater than the first bitwidth, a sign bit, and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. The integer form fractions of the first bitwidths are provided to an adder tree using the first bitwidth, and if the sum has an excess percentage of leading 0s, then the second bitwidth is used by an adder tree using the second bitwidth to form a great precision integer form fraction. The sign, integer form fraction, and maximum exponent are provided to an normalizer which generates a floating point result.

Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller which is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

Abstract: A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates an integer form fraction accompanied by a sign bit and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. A range estimating process determines a possible range of values from the exponent differences and determines an adder precision. A summing process adds all of the integer form fractions using the determined adder precision, and converts the sum to a floating point value using the maximum exponent sum, sign bit of the summed integer form fractions, and optionally performs a 2's complement of the summed integer form fraction if the sign bit is negative.

Abstract: A system and method for a switching network is disclosed. A plurality of first switching assemblies, second switching assemblies and intermediate switching assemblies with each of the first switching assemblies, second switching assemblies and intermediate switching assemblies having at least two input ports and output ports is provided. Selective one of the two input ports is configured to receive a data to be processed and delivered at a designated one of the output ports. Received data passes through one or more selective first switching assemblies, one or more intermediate switching assemblies and one or more selective second switching assemblies, before the received data is delivered to the designated port. A plurality of additional data is received in one or more of the input ports to be delivered to one or more designated output ports is processed before the received data is delivered to the designated one of the output ports.

Abstract: A lightweight node in a decentralized network includes stores a blockchain with a plurality of blocks. The lightweight node adds blocks to the blockchain successively. A given block having a header and a body. The header includes a data merkle root generated as a root hash of a data merkle tree with one or more leaf nodes that are one or more hashes. A given hash being a hash of a combination of (1) a public key associated with a lightweight node of the decentralized network and (2) of a validity value associated with the public key indicating whether the public key is a valid public key. The data merkle root being insufficient for restoring the data merkle tree. But with a public key and an intermediate hash the date merkle root is sufficient for at least partly verifying the public key.

Abstract: A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.