Abstract: A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.

Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: A system and method for a memory device is disclosed. A substrate is provided. A nucleation pad is disposed over the substrate. A nanowire is disposed substantially perpendicular, about a center of the nucleation pad. A charge current is selectively passed through the substrate to nucleate a magnetic vortex in the nucleation pad, the magnetic vortex indicative of a magnetic domain and a direction of the magnetic vortex indicative of a polarity of the magnetic domain. A shift current is applied through the nanowire to shift the magnetic domain into the nanowire.

Abstract: A system and method for a logic device is disclosed. A first substrate, and a second substrate is provided, which are spaced apart from each other and manifests Spin orbit torque effect. A nanomagnet is disposed over the first substrate and the second substrate. A first charge current is passed through the first substrate and a second charge current is passed through the second substrate. A direction of flow of the first charge current and the second charge current defines an input value of either a first value or a second value. A spin in the nanomagnet is selectively oriented based on the direction of flow of the first charge current and the second charge current. The spin in the nanomagnet is selectively read to determine an output value as the first value or the second value. The logic device is configured as a XOR logic.

Abstract: A system and method for a logic device is disclosed. A first nanotrack along a first axis and a second nanotrack along a second axis perpendicular to the first axis are disposed over a substrate. The second nanotrack is disposed over the first nanotrack in a overlap portion. An input value is defined about a first end of the first nanotrack and the second nanotrack by nucleating a skyrmion, wherein a presence of the skyrmion defines a first value and absence of the skyrmion defines a second value. The nucleated skyrmion moves towards the second end of the nanotracks when a charge current is passed through the first nanotrack and the second nanotrack along the second axis. The presence of the skyrmion sensed at the second end of the nanotrack indicates an output value of the first value.

Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable wordline signal pulse width which may be reduced sufficiently to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and a nearly error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline signal pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline signal pulse width with an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

Abstract: A decision feedback equalizer includes a summer, a slicer, and a feedback circuit. The summer is configured to receive an input signal and a correction signal from the feedback circuit and generate a summer output signal. The slicer includes a first slicer and a second slicer, both are configured to receive the summer output signal as an input, and output a slicer output signal. The feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal. The input signal is received at a first clock rate. The first slicer and the second slicer sample the input signal at a second clock rate, about half the first clock rate.

Abstract: An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.

Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

Abstract: A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.

Abstract: A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.

Abstract: A lightweight node in a decentralized network includes stores a blockchain with a plurality of blocks. The lightweight node adds blocks to the blockchain successively. A given block having a header and a body. The header includes a data merkle root generated as a root hash of a data merkle tree with one or more leaf nodes that are one or more hashes. A given hash being a hash of a combination of (1) a public key associated with a lightweight node of the decentralized network and (2) of a validity value associated with the public key indicating whether the public key is a valid public key. The data merkle root being insufficient for restoring the data merkle tree. But with a public key and an intermediate hash the date merkle root is sufficient for at least partly verifying the public key.

Abstract: A dot product multiplier for matrix operations for an A matrix of order 1×m with a coefficient B matrix of order m×m. Processing Elements (PEs) are arranged in an m×m array, the columns of the array summed to provide a dot product result. Each of the PEs contains a sign determiner and a plurality of analog multiplier cells, one multiplier cell for each value bit. The multipliers operate over four clock cycles, initializing a capacitor charge according to sign on a first clock phase, sharing charge on a second phase, canceling charge on a third phase, and outputting the resultant charge on a fourth phase, the resultant charge on each column representing the dot product for that column.

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

Abstract: A process for performing vector dot products receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The process generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits to form a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information including MAX_EXP and EXP_DIFF. A second pipeline stage receives the multiplied pairs of normalized mantissas, optionally performs an exponent adjustment, pads, complements and shifts the normalized mantissas, and the results are added in a series of stages until a single addition result remains, which is normalized using MAX_EXP to form the floating point output result.

Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

Abstract: A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).

Abstract: A master processor is configured to execute a first thread and a second thread designated to run a program in sequence. A slave processor is configured to execute a third thread to run the program in sequence. An instruction fetch compare engine is provided. The first thread initiates a first thread instruction fetch for the program and stored in an instruction fetch storage. Retrieved data associated with the fetched first thread instruction is stored in a retrieved data storage. The second thread initiates a second thread instruction fetch for the program. The instruction fetch compare logic compares the second thread instruction fetch for the program with the first thread instruction fetch stored in the instruction fetch storage for a match. When there is a match, the retrieved data associated with the fetched first thread instruction is presented from the retrieved data storage, in response to the second thread instruction fetch.

Abstract: An exemplary multi-threaded memory management system comprises a memory management unit (MMU) configured with a plurality of physical address (PA) output ports individually dedicated to a respective plurality of threads, wherein the MMU is configured to adjust scheduling of the plurality of threads based on the status of an item requested from a cache. The MMU may be configured to translate a virtual address (VA) input from an individual thread to a PA output on the respective PA output port. The cache may be a translation look-aside buffer. The item requested from the cache may be in transient status when a response is expected or valid status when the response is received. The MMU may signal a thread scheduler to run a thread when a requested item's status becomes valid, permitting stalling individual threads without blocking other threads that continue running using the PA output port dedicated to each thread.

Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.