Abstract: In some implementations, a satellite may include a software-defined radio (SDR), antenna circuits, and front-end circuits. Each antenna circuit may include a first antenna and a second antenna. Each front-end circuit may be coupled between the SDR and one of the plurality of antenna circuits and may include a transmit path, a first receive path, and a second receive path. The transmit path may include an input coupled to an output of the radio and an output selectively coupled to the first antenna for ISL and TT&C transmissions. The first path includes an input to couple to the first antenna and an output to couple to the radio. The second path includes an input coupled to the second antenna and an output to couple to the radio. The front-end circuit may selectively enable one of the first or second receive paths for ISL or TT&C communications.

Abstract: A system may include an analog front-end circuit configured to receive signals from an antenna array and a digital circuit coupled to the analog front end. The digital circuit may include a digital beamforming circuit configured to include a Nyquist fractional delay filter that is piecewise continuous in the frequency domain. The Nyquist fractional delay filter may be implemented as a Gaussian Nyquist filter, a generalized raised cosine Nyquist filter, or another Nyquist filter. The fractional delay filter may be critically sampled and evaluated numerically or with a closed-form time-domain expression. The fractional delay filter may be part of a digital beamforming phased array antenna system.

Abstract: The required equivalent isotropic radiated power of a phased array can vary rapidly due to changes of channel conditions, link properties, communication distance, or mode of operation. Maintaining maximum efficiency of a phased array antenna over the entire range of required equivalent isotropic radiated power levels is challenging but highly desirable. An array controller is disclosed that computes the optimal set of power amplifiers and beamformer elements to be activated in order to achieve the highest possible efficiency, or equivalently, the lower possible power consumption for the equivalent isotropic radiated power while maintaining the selected beam pattern.

Abstract: A system may include a smart user (UE) device that includes one or more network interfaces and a processor coupled to the network interfaces. The network interfaces may include a first network interface configured to communicate with a satellite constellation and a second network interface configured to communicate with one or more gateways that are communicatively coupled to a core network. The processor may be configured to operate as a virtual gateway to forward data for other users between the core network and the satellite constellation. The smart UE device may allow a communication system to take advantage of available uplink and downlink bandwidth of one or more UE devices to distribute the data transmission load, thereby improving data throughput of the system.

Abstract: An integrated circuit may include a phase shifting/partial beamforming network circuit and a plurality of true time delay (TTD) circuits. The beamforming circuit may include a plurality of receive inputs. Each receive input may be coupled to one of a plurality of antenna elements. The beamforming circuit may include a plurality of receive/transmit connectors, each of which may correspond to a beam of a plurality of beams. The beamforming circuit may include a plurality of transmit outputs each of which may be coupled to one of the plurality of antenna elements. Each TTD circuit may include a first connection coupled to one of the receive/transmit connector outputs and a second connection coupled to one of a plurality of serial lines. Each TTD circuit may be configured to apply one or more of an integer delay or a fractional delay to data received from the receive/transmit connector or the serial line.

Abstract: A system may include a digital beamformer (DBF) circuit coupled to N antenna elements of an analog front end. The DBF circuit may include a plurality of digital pre-distortion (DPD) blocks and a controller. Each DPD block may correspond to a transmission path that includes one of the N antenna elements. The controller may be configured to determine one or more parameters associated with the analog front end, selectively activate some, but not all, of the plurality of DPD blocks, and determine DPD data from the one or more DPD tables for each activated DPD block based on the one or more parameters. The controller may independently configure each activated DPD block with the determined DPD data to pre-compensate a signal on a per antenna element basis to negate non-linearities. These DPD Blocks can be independently configured to realize phased array architectures with reduced antenna array power consumption and heating.

Abstract: A phased array antenna device may include a base including circuitry configured to couple to a backplane and a plurality of circuit cards arranged in parallel and coupled to circuitry of the base. Each circuit card may include an array of circularly polarized unit antenna elements integrated into the circuit card and arranged along an edge of the circuit card. Each circularly polarized unit antenna element of the array may be configured to radiate and receive electromagnetic signals directly from the edge of the circuit card. In some implementations, the edge of each circuit card may include a plurality of substrate extensions with chamfered edges formed from a substrate of the circuit card. At least a portion of some of the chamfered edges may include a metal coating.

Abstract: A system may include multiple digital beamformer (DBF) circuits coupled to an analog front end that includes an antenna array. Each DBF circuit is coupled to a subset of the antenna elements of the array. Each DBF may be configured to adjust coefficients of complex multipliers to selectively enable and disable beams, antenna elements, transmit paths, receive paths, or any combination thereof to enable per-element calibration of the antenna array.

Abstract: A circuit may include an input to receive a signal corresponding to a radio frequency signal received at each element of an antenna array. The circuit may include a beamforming circuit configured to determine two or more samples of a symbol period of the signal from each antenna element and to determine the error estimates for each antenna element based on the two or more samples. The beamforming circuit may be configured to determine one of a line or a plane that best fits the error estimates; determine a direction of arrival of the radio frequency signal based on one or more parameters of the line or the plane and determine a fractional delay for each antenna element based on the direction of arrival of the radio frequency signal.

Abstract: A phased array antenna device may include a base including circuitry configured to couple to a backplane and a plurality of circuit cards arranged in parallel and coupled to circuitry of the base. Each circuit card may include an array of circularly polarized unit antenna elements integrated into the circuit card and arranged along an edge of the circuit card. Each circularly polarized unit antenna element of the array may be configured to radiate and receive electromagnetic signals directly from the edge of the circuit card. In some implementations, the edge of each circuit card may include a plurality of substrate extensions with chamfered edges formed from a substrate of the circuit card. At least a portion of some of the chamfered edges may include a metal coating.