Abstract: A system and method of implementing thereof that maps and condenses system control using reachable state control words is described. The system includes a control logic block, a look-up table which stores N-bit reachable state control words derived from an implementation description N-bit control signal, and a logic hardware block. The control logic block accesses the look-up table with a M-bit control word address. The accessed look-up table outputs a N-bit reachable state control word which is used to control the logic hardware block so as to simulate functions as defined by a user input description. A method for implementing the system is performed by synthesizing the user input description to generate an implementation description which describes a control model of the system in terms of a control logic block driving a logic hardware block with a N-bit control signal. The implementation description is analyzed to determine the reachable states of the N-bit control signal.

Abstract: A configuration bit layout for a reconfigurable chip includes address bits stored along with configuration bits. The blocks of data are loaded onto the reconfigurable chip from an external memory and the address information is decoded to load the configuration bits onto the correct locations in the reconfigurable chip. In this way, configuration data need not be stored sequentially in the external memory. Configurations can be allocated into different slices of the reconfigurable chip as well.

Abstract: A reconfigurable chip includes data registers which can be loaded from off-chip or on-chip. The data register comprises a register block produced from a number of register block units. The register bock units include an active plane store storing the current value of the register bit, at least one off-chip data background store storing a data bit which can be loaded from off-chip, and at least one on-chip data background store storing a value which can be loaded from on-chip.

Abstract: A system and method of detecting events such as DMA requests, computation operations, configuration set-up operations, occurring in a processing system which are performed by functional system blocks within the system by using logic flags stored in registers within each of the functional system blocks. The registers are coupled to the CPU on dedicated signal lines. Each time a functional block completes an operation or function it updates its corresponding logic flag. The CPU monitors the state of the flags to determine whether certain events have taken place in the system in order to sequentially coordinate functions and operations within the system without the use of interrupt signals on the system bus.

Abstract: A reconfigurable system is arranged to have separate control and the data paths. The control path is set up using control fabric units which use an associated state machine to produce an address to a functional unit memory. The functional unit memory then produces the configuration data for the functional units. The use of a state machine allows for a very dense, highly-sequencable control unit that provides an encoded state to a memory which then allows a high number of control terms which results in a more linear interconnection to the data path units.

Abstract: A memory access system is described in which local memory units on a reconfigurable chip can be used in conjunction with the system memory. Data path units on the reconfigurable chip can cause data to be swapped in and out of the local memory units as a result of calculations within the reconfigurable fabric. Alternately, a cache-like system can be used so that the data can be read into the local memory unit from the system memory units automatically.

Abstract: A system and method of increasing the efficiency of a data processing system by alternately streaming portions of a large block of data from a large memory area into two memory banks within a smaller memory area using consecutive DMA transactions. Each streaming DMA transaction is entered in a DMA transaction queue and once it becomes active, transfers a block of data, the same size as one of the two memory banks, into one of the memory banks, after which it becomes inactive and is re-entered in the queue. When the streaming DMA transaction becomes active again, it switches to a different memory bank address and continues in the large data block where it stopped last time it was active. The streaming DMA transaction continues to be circulated in the queue until a total number of transaction iterations is reached, at which point the streaming DMA transaction is complete and is removed from the queue.

Abstract: A reconfigurable programmable sum of products generator allows for multiple configurations to be associated with a programmable sum of products generator. These configurations can be modified by changing the configurations in an associated configuration memory for the programmable sum of products generator. By using a reconfigurable programmable sum of products generator structure, a dense and highly interconnected logic is produced. Such a dense and highly interconnected logic is particularly valuable for use in the control path of a reconfigurable system.

Abstract: A system and method of logic synthesis uses a behavioral synthesis tool to convert a behavioral language description (e.g., behavioral description code, an intuitive algorithm, or programming language description) of an ASIC into a partitioned RTL language description including RTL sub-descriptions corresponding to each of control, datapath, and memory. Each of the higher level RTL sub-descriptions is then mapped directly (i.e., a one-to-one mapping correspondence) to re-configurable silicon structures without requiring an RTL synthesis tool to translate the RTL description into individual standardized cell logic gates and interconnect level description. The silicon structures are controlled by the RTL sub-descriptions to provide a direct synthesized physical implementation of the ASIC thereby providing a single step synthesis method of going from a behavioral description to a synthesized silicon implementation.

Abstract: A configuration state memory is associated with a configurable functional block on a reconfigurable chip. The configuration state memory stores more than one configuration for the functional block. This allows the functional block to switch configurations without requiring the configuration data to be loaded from off-chip which would stall the operation of the reconfigurable chip. In a preferred embodiment, the configuration state memory uses a relatively few address bits to produce a relatively broad configuration output to the functional blocks. The small number of input address bits allows the configuration state memory to be addressed by relatively small state machine unit.

Abstract: The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable “hard-wired” functions.

Abstract: An apparatus and method of performing random bit swapping including bit (single bit) swapping, nibble (4-bit) swapping, byte (8-bit) swapping, and half word (16-bit) swapping including a matrix of rows of two-to-one multiplexers. Each row of multiplexers shares the same control signal such that all of the multiplexer in a given row either outputs a “non-swapped” bit value or a “swapped” bit value. In addition, multiplexers are grouped within rows to allow 2-bit, 4-bit, 8-bit, and n-bit swaps in each consecutive row. Depending on the shared multiplexer controls for each row, the matrix can be programmed to perform any swapping function or possible bit pattern. The number of bits output by the matrix determines the number of rows used, e.g., an 8-bit dataword uses 3 rows, 16-bit word uses 4 rows, 2N-bit word uses N rows.