Abstract: A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.

Abstract: An anti-fuse array structure, an operation method thereof and a memory are provided. The anti-fuse array structure includes an anti-fuse array area and a selection circuit area. The anti-fuse array area includes a plurality of anti-fuse cells, and the selection circuit area includes a plurality of selection transistors. The selection circuit area is located on at least one side of the anti-fuse array area.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes: forming a first patterned mask layer on an upper surface of a first filling dielectric layer, the first patterned mask layer including a plurality of pattern units; etching the first filling dielectric layer based on the first patterned mask layer to form etched recesses; forming a second filling dielectric layer, the second filling dielectric layer filling up the etched recesses and covering the first patterned mask layer; removing the first patterned mask layer, and parts of the second filling dielectric layer on the first patterned mask layer and between the pattern units; removing the remaining first filling dielectric layer to form a plurality of capacitor contact holes exposing the substrate; and forming, in the capacitor contact holes, capacitor contact structures located on the two opposite sides of the BLs.