Abstract: A filter (201) accepts spreading code sequences or the like as input sequences of a chip rate 1/D, the accepted spreading code sequences are sequentially delayed and distributed by delay circuits (202) connected in series, delay times of individual signals are an arithmetical progression with a chip length D being a common difference D, the individual signals are amplified with spreading codes by amplifiers (203), amplification factors for the individual signals are a geometrical progression of a common ratio r, the sum of the amplified signals is obtained by addition in an adder (204), and the result is sequentially output as an output sequence.