Abstract: A new method and apparatus is provided that assures constant fluid flow of the fluid that is entered into a semiconductor device processing tank or container. A flow meter is set to a particular flow rate; the fluid that comes from the POU is routed through the flow meter. The fluid passes through a flow meter into a processing tank. The fluid is allowed to fill the container up to an overflow point of the container. An overflow basin is provided into which the overflowing fluid is routed from where the fluid is drained into a fluid reclaim vessel. The overflow is detected by a sensor, the sensor activates an overflow relieve valve that is mounted in the bottom of the container. The overflow relieve valve is opened and drains fluid from the container thus counteracting the overflow of the fluid into the overflow basin. The interaction between the overflow detector and the overflow relieve valve assures a constant rate of supply of the fluid to the processing tank or container.

Abstract: A method for forming integrated circuit device structures upon active semiconductor regions of a semiconductor substrate. The active semiconductor regions are defined by Field OXide (FOX) isolation regions which are formed through a Polysilicon Buffered LOCal Oxidation of Silicon (PBLOCOS) oxidation mask structure. The PBLOCOS oxidation mask structure includes a blanket pad oxide layer which resides upon the semiconductor substrate, a blanket polysilicon buffer layer which resides upon the blanket pad oxide layer and a patterned silicon nitride layer which resides upon the blanket polysilicon buffer layer. Portions of the blanket polysilicon buffer layer and the blanket pad oxide layer exposed through the patterned silicon nitride layer are completely consumed to leave remaining the patterned silicon nitride layer, a patterned polysilicon buffer layer and a patterned pad oxide layer upon the active regions of the semiconductor substrate which are separated by the FOX isolation regions.

Abstract: A process has been developed which allows contact between levels of interconnect metallization structures, to occur without the use of via holes, etched in interlevel insulator layers. The process features creation of a raised tungsten plug structure, used to provide contact between underlying active device regions and an overlying interconnect metallization structure. The tungsten plug structure is formed by photolithographic masking and dry etching procedures, thus avoiding increasing the size of a tungsten seam, in the center of the plug structure. In addition the tungsten definition process, also results in a raised plug structure, allowing subsequent contact of interconnect metallization levels to proceed without the use of etched via holes in interlevel insulator layers.

Abstract: A method, and resultant structure, for manufacturing large highly reflective metal reflector plates on an integrated circuit chip, for applications in game chips or similar virtual image projection systems, is described. A metal interconnection layer is formed above a semiconductor substrate, an intermetal dielectric layer is formed on the metal interconnection layer, and an opening is made through the intermetal dielectric layer to expose a portion of the metal interconnection layer. A first metal layer is formed on the intermetal dielectric layer and connecting to the metal interconnection layer through the opening. A second metal layer is formed on the first metal layer. A third metal layer is formed on the second metal layer. A highly reflective metal layer is formed on the third metal layer. The the first, second, third and highly reflective metal layers are patterned to form the highly reflective metal reflector plate.

Abstract: The method of manufacture of a PMOS integrated circuit having a feature size in the order of one micron or less is done by providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric. Implanting of BF.sub.2 + ions and B11+ ions sequentially by using the pattern as a mask. The structure is annealed at more than about 850.degree. C. to complete the PMOS integrated circuit. This method results in lower contact resistance to the P+ regions and lower sheet resistance for higher speed CMOS integrated circuits at minimal increase of manufacturing cost.