Abstract: A new method for preventing intermittent high Kelvin via resistance is achieved. This is accomplished by lowering the chamber pressure during warm-up, which prevents the wafer temperature from rising above about 380° C. The present invention uses a pressure of between 2 and 3 Torr during warm-up of the wafer prior to barrier metal deposition rather than 5 Torr, which is conventionally used. Using the conventional pressure of 5 Torr the wafer temperature overshoots to about 395° C. before settling to about 380° C. By reducing the pressure to between 2 and 3 Torr, the thermal conductivity between the wafer heater and the wafer is reduced and the overshoot reduced or eliminated. The lower temperature reduces the deposition rate by approximately 10 angstroms over a 15 second deposition, but this is compensated for by an increase in deposition time. However, because the reaction is carried out in the reaction-limited regime, the step coverage will increase when wafer temperature is reduced.

Abstract: An improved manufacturing system for processing semiconductor wafers which includes a (1) plurality of processing stations, (2) a sealed transport tunnel located directly over the processing stations, (3) a transport to move wafers within the tunnel, (4) interconnection chambers joining the transport tunnel and the processing stations, (5) interface mechanisms in the interconnection chambers to move the wafers to and from the processing stations, and (6) a computer to control the operations of the transport, the interface mechanisms, and the processing equipment at the processing stations.

Abstract: A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

Abstract: A wafer orienting apparatus for aligning a plurality of semiconductor wafers each of which bas a v-notch formed on its outer periphery. The apparatus includes a cassette process carrier for supporting the plurality of wafers in parallel wafer supporting slots and wafer support means engaging the periphery of each wafer in an individual slot with the central axis of all wafers in coaxial alignment. A supporting platform is placed over the cassette for supporting the wafers in an inverted position in which the wafers are substantially vertical and biased by their own weight against a multiplicity of orienting mechanisms. The orienting mechanisms are arranged to correspond to each wafer position within the cassette. The plurality of orienting mechanisms are intergrated with the supporting platform so that all wafers within the cassette can be aligned during this aligning process.

Abstract: A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

Abstract: A method of fabricating gate oxides of different thicknesses has been achieved. Active area isolations are provided in a silicon substrate to define low voltage sections and high voltage sections in the silicon substrate. A sacrificial oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the sacrificial oxide layer. A masking oxide layer is deposited overlying the silicon nitride layer. The masking oxide layer is patterned to form a hard mask overlying the low voltage sections. The silicon nitride layer is etched through where exposed by the hard mask thereby exposing the sacrificial oxide layer overlying the high voltage section. The exposed sacrificial oxide layer and the hard mask are etched away. A thick gate oxide layer is grown overlying the silicon substrate in the high voltage section. The silicon nitride layer is etched away. The sacrificial oxide layer overlying the low voltage section is etched away.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A improved and new method for forming dual damascene etch back of copper lines and interconnects (studs) using a combination of oxidation of Cu and chemical/mass transport of the Cu oxide by the action of acid. The etch back solves the dishing problem in that it planarized the Cu. Etch back rates can be high at high temperatures. The surface of the substrate is kept clean and free of polishing scratches from CMP. The process produces better uniformity across the substrate and better electrical performance due the increased copper line cross-sectional area.

Abstract: An apparatus for adjusting a measure of liquid for mixing with a second liquid which includes an adjustable overflow tube cooperating within a closed tank. The tank has a threaded top port and a sleeved bushing bottom port. The top and bottom ports are axially in alignment. The overflow tube has a sidewall defining a bore. The sidewall has a smooth outside surface on one end and a length of external thread cut on the other end. This length of external thread is preceded by a "T" handle for turning the overflow tube and proceeded by an overflow aperture through the side wall. The smooth end of the adjustable overflow tube is inserted through the threaded top port into the sleeve bushing of the bottom port for a leak-proof fit thereafter, engaging with the threaded top port. The overflow tube is rotated to translate the overflow tube until the overflow aperture reaches a desired level.

Abstract: A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening.

Abstract: A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.

Abstract: The present invention provides a method of forming closely spaced interconnections over a semiconductor structure using conventional photolithographic and etching methods and tools. The process which begins by providing an insulating layer 14 over a semiconductor structure 10. A conductive layer and an isolation layer are sequentially formed over the insulating layer 14. The conductive layer is patterned forming spaced first interconnects 16 covered by isolation layer blocks 20. Sidewall spacers are then formed on the sidewalls of the first interconnects and the isolation layer blocks 20. A second conductive layer is formed over the resulting surface. The second conductive layer is planarized forming second interconnects 30 and excess conductive pieces 31 between the sidewall spacers. The excess conductive pieces 31 are intended to be removed.

Abstract: A method of stripping photoresist and polymer from a wafer after a dry etch of a nitrade or a polysilicon layer that immerses the wafer in a peroxydisulfate (S.sub.2 O.sub.8.sup.2-)/HCl wet bath and while the wafer is still immersed, irradiates the wafer with a UV laser. The method comprises: (a) forming an silicon nitride layer 24 and a photoresist pattern 28 over a semi conductor structure 10; (b) dry etching the silicon nitride layer 24 thus forming a polymer 30 over the photoresist pattern, and the silicon nitride layer, (c) Immersing the substrate, the photoresist pattern, the polymer 30 in a liquid bath 34 comprising (1) peroxydisulfate (S.sub.2 O.sub.8.sup.2-), (2) HCl, and (3) water; and irradiating the photoresist pattern 28 and polymer layer 30 with a UV laser thereby removing the photoresist 28 and polymer 30.

Abstract: Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon oxynitride layer is placed over a polysilicon gate with conventional sidewalls and insulative cap. In another embodiment the insulative cap and the sidewalls are formed of a silicon enriched silicon oxinitride. Etching of contact openings in the subsequently deposited insulative layer is suppressed by the silicon enriched silicon oxynitride if it is engaged because of a mis-aligned contact mask. In another embodiment a polysilicon stack edge of a memory device is protected by a conformal silicon oxynitride layer during etching of a self-aligned-source (SAS) region. These embodiments are accomplished with minimal and virtually negligible increase in process complexity or cost.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

Abstract: A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

Abstract: An N-Channel Metal Oxide Semiconductor Field Effect Transistor (N-MOSFET) with minimum susceptibility to the Hot Carrier Effect (HCE) and a method by which the N-MOSFET is fabricated. Formed upon a semiconductor substrate is a N-MOSFET structure including a gate oxide upon a semiconductor substrate, a gate electrode upon the gate oxide and a pair of N+ source/drain regions adjoining the gate electrode and the gate oxide. Implanted into the gate oxide regions beneath the gate electrode edges is a dose of a hardening ion. The hardening ion may be either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt angle ion implant process. Optionally, a Lightly Doped Drain (LDD) source/drain electrode structure or Double Doped Drain (DDD) source/drain electrode structure may be incorporated into the N-MOSFET structure.