Abstract: A improved and new method for forming dual damascene etch back of copper lines and interconnects (studs) using a combination of oxidation of Cu and chemical/mass transport of the Cu oxide by the action of acid. The etch back solves the dishing problem in that it planarized the Cu. Etch back rates can be high at high temperatures. The surface of the substrate is kept clean and free of polishing scratches from CMP. The process produces better uniformity across the substrate and better electrical performance due the increased copper line cross-sectional area.

Abstract: The present invention provides a method of forming closely spaced interconnections over a semiconductor structure using conventional photolithographic and etching methods and tools. The process which begins by providing an insulating layer 14 over a semiconductor structure 10. A conductive layer and an isolation layer are sequentially formed over the insulating layer 14. The conductive layer is patterned forming spaced first interconnects 16 covered by isolation layer blocks 20. Sidewall spacers are then formed on the sidewalls of the first interconnects and the isolation layer blocks 20. A second conductive layer is formed over the resulting surface. The second conductive layer is planarized forming second interconnects 30 and excess conductive pieces 31 between the sidewall spacers. The excess conductive pieces 31 are intended to be removed.

Abstract: A method of stripping photoresist and polymer from a wafer after a dry etch of a nitrade or a polysilicon layer that immerses the wafer in a peroxydisulfate (S.sub.2 O.sub.8.sup.2-)/HCl wet bath and while the wafer is still immersed, irradiates the wafer with a UV laser. The method comprises: (a) forming an silicon nitride layer 24 and a photoresist pattern 28 over a semi conductor structure 10; (b) dry etching the silicon nitride layer 24 thus forming a polymer 30 over the photoresist pattern, and the silicon nitride layer, (c) Immersing the substrate, the photoresist pattern, the polymer 30 in a liquid bath 34 comprising (1) peroxydisulfate (S.sub.2 O.sub.8.sup.2-), (2) HCl, and (3) water; and irradiating the photoresist pattern 28 and polymer layer 30 with a UV laser thereby removing the photoresist 28 and polymer 30.

Abstract: Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon oxynitride layer is placed over a polysilicon gate with conventional sidewalls and insulative cap. In another embodiment the insulative cap and the sidewalls are formed of a silicon enriched silicon oxinitride. Etching of contact openings in the subsequently deposited insulative layer is suppressed by the silicon enriched silicon oxynitride if it is engaged because of a mis-aligned contact mask. In another embodiment a polysilicon stack edge of a memory device is protected by a conformal silicon oxynitride layer during etching of a self-aligned-source (SAS) region. These embodiments are accomplished with minimal and virtually negligible increase in process complexity or cost.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

Abstract: A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

Abstract: An N-Channel Metal Oxide Semiconductor Field Effect Transistor (N-MOSFET) with minimum susceptibility to the Hot Carrier Effect (HCE) and a method by which the N-MOSFET is fabricated. Formed upon a semiconductor substrate is a N-MOSFET structure including a gate oxide upon a semiconductor substrate, a gate electrode upon the gate oxide and a pair of N+ source/drain regions adjoining the gate electrode and the gate oxide. Implanted into the gate oxide regions beneath the gate electrode edges is a dose of a hardening ion. The hardening ion may be either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt angle ion implant process. Optionally, a Lightly Doped Drain (LDD) source/drain electrode structure or Double Doped Drain (DDD) source/drain electrode structure may be incorporated into the N-MOSFET structure.