Abstract: A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first conductive layer is deposited. An interpoly oxide layer is deposited. A second conductive layer is deposited. The second conductive layer, the interpoly oxide layer, the first conductive layer, and the tunneling oxide layer are patterned to form control gates and floating gates. Ions are implanted to form drain junctions. A mask protects the planned source junctions. The drain junctions are opposite type to the semiconductor substrate. Ions are implanted to form source junctions. A mask protects the drain junctions. The source junctions are opposite type to the semiconductor substrate. Ions are implanted to form channel stop junctions to complete the Flash EEPROM memory cells.

Abstract: A method of fabricating multiple thickness gate oxide layers, comprising the following steps. A silicon substrate having at least a first and second gate oxide region is provided. A first gate oxide layer is formed over the silicon substrate within the first gate oxide region. The first gate oxide layer having a first predetermined thickness. A first layer of polysilicon is deposited and planarized over the first gate oxide layer. The first planarized layer of polysilicon and the first gate oxide layer are masked and etched within the second gate oxide region, exposing the silicon substrate within the second gate oxide region. A second gate oxide layer is formed over the exposed silicon substrate within the second gate oxide region. The second gate oxide layer having a second predetermined thickness. A second layer of polysilicon is selectively deposited over the second gate oxide layer. The first and second layers of polysilicon are planarized to a uniform thickness.

Abstract: A cylindrical semiconductor capacitor and manufacturing method is provided which starts by taking an oxide layer which is formed over a semiconductor substrate and simultaneously removing a cylindrical volume and a toroidal volume around the cylindrical volume. The removed cylindrical and toroidal volumes are filled with a copper/tantalum nitride conductor to form a metal cylinder and ring. An oxide ring between the conductive cylinder and ring is removed. A high dielectric constant material is formed to replace the oxide ring between the metal cylinder and ring to form a cylindrical capacitor. Additional oxide material is deposited, patterned, and filled with copper/tantalum nitride conductor a to make a first connection to the metal ring, and a further dielectric is deposited, patterned, and filled with additional copper/tantalum nitride conductor to form a second connection to the metal cylinder.