Patents Assigned to Chartered Semiconductor Maufacturing Ltd.
  • Patent number: 6558994
    Abstract: A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: May 6, 2003
    Assignee: Chartered Semiconductors Maufacturing Ltd.
    Inventors: Randall Cher Liang Cha, Yeow Kheng Lim, Alex See, Tae Jong Lee, Wang Ling Goh
  • Patent number: 6306721
    Abstract: A new method is provided for the creation of a salicided polysilicon capacitor. A salicided layer of polysilicon is created as the lower plate of a salicided polysilicon capacitor over the surface of a field isolation region. A layer of silicon nitride is deposited over the field oxide isolation region including the surface of the salicided polysilicon layer. A layer of TEOS is deposited over the surface of the layer of silicon nitride, a layer if titanium nitride is deposited over the surface of the layer of TEOS. The layer of TiN is etched after which the layer of TEOS is etched. The etch of the layer of TEOS is an overetch whereby TEOS is symmetrically removed from underneath the etched layer of TiN, leaving remnants of TEOS in place underneath the etched layer of TiN while at the same time creating air gaps underneath the etched layer of TiN.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: October 23, 2001
    Assignee: Chartered Semiconductor Maufacturing Ltd.
    Inventors: Yeow Meng Teo, Madhusudan Mukhopadhyay, Heng Jee Kiat