Patents Assigned to Chartered Semiconductors Manufactured Limited
  • Patent number: 6899857
    Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: May 31, 2005
    Assignee: Chartered Semiconductors Manufactured Limited
    Inventors: Soo Choi Pheng, Lap Chan, Wang Cui Yang, Siew Yong Kong, Alex See
  • Publication number: 20030096499
    Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 22, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Guy Eristoff, Sarion C.S. Lee, Liew San Leong, Goh Khoon Meng
  • Publication number: 20030092281
    Abstract: A method for etching an organic bottom antireflective coating (OBARC) and a photoresist material in a single etching process. The method comprises the steps of etching the OBARC and trimming the photoresist material at the same time in an etching environment using a substantially isotropic etching operation. The etching environment including an etching chamber with a top electrode and a bottom electrode wherein a mixture of abrasive gases can flow therethrough. Using an endpoint detection test to determine when an exposed portion of OBARC has been removed, the exposed portion of OBARC being an area of OBARC without photoresist protection and exposed to the etching environment. Applying an over-etch step to trim the photoresist to a desired dimension where the time of the over-etch step being based on the percentage of an endpoint time and the process condition of the over-etch step being same as that of the endpoint step.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Pradeep Yelehanka Ramachandramurthy, Jie Yu, Loh Wei Loong, Chen Tong Qing
  • Publication number: 20030092251
    Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Soo Choi Pheng, Lap Chan, Wang Cui Yang, Siew Yong Kong, Alex See
  • Publication number: 20030092258
    Abstract: A light shield apparatus and formation method for preventing the transmission of incident light towards active devices of the display. In one embodiment, the present invention recites forming a plurality of metal pixels wherein adjacent ones of the plurality of metal pixels have a gap region disposed therebetween. The present embodiment then recites depositing a light absorbing antireflective coating material within the gap region to form a light shield such that transmission of incident light through the gap region towards underlying active devices is reduced. Hence, the present embodiments also reduce problems associated with Liquid Crystal alignment difficulty and passivation integrity (cracking of thin passivation). Next, the present embodiment deposits a thin composite passivation layer above the plurality of metal pixels and the antireflective coating material.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventor: Xavier Seah Teo Leng
  • Publication number: 20030092276
    Abstract: A method for removing a silicide poly on an integrated circuit (IC) chip. Specifically, one embodiment of the present invention discloses a method for exposing a gate oxide layer with a fluorine based reactive ion etching (F-based RIE) process and immersion in a sodium hydroxide based solution. The F-based RIE damages a silicide layer that covers a polysilicon gate layer. Damage to the silicide layer allows for penetration of chemicals to a polysilicon gate layer. Immersion of the IC chip in the sodium hydroxide based solution etches away the polysilicon gate layer and lifts off the silicide layer without altering an underlying gate oxide layer. Also, another embodiment uses a solution including sodium hydroxide and sodium chloride. As such, failure analysis of the gate oxide layer can proceed without concern for damage due to the removal process.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Song Zhigang, Guo Zhi Rong, Shailesh Redkar, Hua Younan
  • Publication number: 20030092284
    Abstract: A method and apparatus for preventing plasma induced damage resulting from high density plasma deposition processes. In the present embodiment, Un-doped Silica Glass(USG) is deposited so as to form a USG liner. In the present embodiment, the USG liner directly overlies a conductive interconnect structure that couples to semiconductor devices that are susceptible to plasma-induced damage during high density plasma deposition processes. A silicon-rich oxide is deposited in-situ immediately following the deposition of the USG liner so as to form a silicon-rich oxide liner that directly overlies the USG liner. The silicon-rich oxide liner protects the interconnect structure during the subsequent high density plasma deposition process, preventing damage resulting from plasma charge to the interconnect structure.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURED LIMITED
    Inventors: Liu Huang, John Suodijono
  • Publication number: 20030090600
    Abstract: A light shield apparatus and formation method for preventing the transmission of incident light towards active devices of the display. In one embodiment, the present invention recites patterning a second metal layer to form a plurality of second metal structures. The present embodiment also recites depositing an intermetal dielectric layer above the plurality of second metal structures. Subsequently, the present embodiment deposits a light absorbing antireflective coating material above the intermetal dielectric layer to form a light shield followed by another planarized IMD layer such that transmission of incident light towards underlying active devices is reduced. The present embodiment also performs the step of forming a plurality of metal pixels above the antireflective coating material wherein adjacent ones of the plurality of metal pixels have a gap region disposed therebetween.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Xavier Seah Teo Leng, Chivukula Subrahmanyam
  • Publication number: 20030092259
    Abstract: In one embodiment, the present invention recites forming a number of first openings in a first substrate. The present embodiment then recites forming a copper region within each first openings during a damascene process, wherein each copper region has a top surface. The present embodiment then disposes a dielectric layer proximate to the top surface of each of the first copper regions during the damascene process. After depositing a second substrate over the dielectric, a number of second openings in a second substrate are made. Next, a number of second copper regions are formed in the second openings, during the damascene process. The dielectric region is thus disposed between the first copper regions and the second copper regions. In so doing, the dielectric region forms a dielectric barrier between the first copper regions and the second copper regions such that a metal-insulator-metal (MIM) capacitor is formed during a damascene process.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Chit Hwei Ng, Chaw Sing Ho
  • Publication number: 20030092240
    Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Siew Yong Kong, Alex See, Simon Chooi, Gautam Sarkar