Abstract: An apparatus includes a pseudo address decoder, a programmable logic array, a corresponding value calculation module, a storage element, a subtracter, and a multiplexer. The pseudo address decoder determines a block corresponding to an index of the compression encoding table. The programmable logic array calculates related data of the block determined by the pseudo address decoder. The corresponding value calculation module calculates the corresponding value in accordance with the related data of the block. Non-repeating or non-increasing data of the compression encoding table are stored in the storage element. The subtracter outputs a difference between the index and the address offset in order to read the storage element. The multiplexer selectively outputs the output values calculated by the corresponding value calculation module or the data read from the storage element.

Abstract: The invention relates to a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which samples the lower frequency write-enable signal at both positive and negative edges of the higher frequency clock. If the sampling result at the positive or negative edge of the higher frequency clock is “1”, the state is recorded to be a “lock state” and no sampling is taken from the next opposite edge. If the sampling result at the positive or negative edge is “0”, the state is recorded to be a “sampling state” and the next opposite edge will be sampled. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.