Abstract: An array substrate includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; and a first voltage supply line, a second voltage supply line, and a third voltage supply line configured to provide a constant voltage signal respectively to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit. The first voltage signal line crosses over a second capacitor electrode in the first pixel driving circuit by a first overlapping area. The second voltage supply line crosses over a second capacitor electrode in the second pixel driving circuit by a second overlapping area. The third voltage supply line crosses over a second capacitor electrode in the third pixel driving circuit by a third overlapping area. The third overlapping area is greater than the first overlapping area, and is greater than the second overlapping area.

Abstract: A shift register unit, configured to generate a first gate drive signal and a second gate drive signal, which includes a first control circuit, configured to control a potential of a first node; a second control circuit, configured to control a potential of a second node; a first output circuit, configured to generate the first gate drive signal based on a first voltage signal provided by a first voltage terminal under the control of the potentials of the first and second nodes, and output the first gate drive signal through a first gate drive signal output terminal, wherein the first voltage signal provided by the first voltage terminal is a high level signal; and a second output circuit, configured to generate a second gate drive signal based on a second voltage signal provided by a second voltage terminal under the control of a potential of a control node, and output the second gate drive signal through a second gate drive signal output terminal.

Abstract: A method for image display in a display apparatus is provided. The method includes displaying an image in a respective subpixel in an image display phase. In a sensing phase subsequent to the image display phase, the method further includes providing an initial voltage signal to an anode of a respective light emitting element in the respective subpixel for a first period of time; allowing the anode of a respective light emitting element to discharge for a second period of time, upon discontinuation of the initial voltage signal; obtaining a residual voltage signal at the anode of the respective light emitting element at an end of the second period of time by a sensing sub-circuit of a respective pixel driving circuit; and transmitting the residual voltage signal to an integrated circuit.

Abstract: A display substrate and related devices are provided. The display substrate includes a plurality of first sub-pixels, second sub-pixels and third sub-pixels. In a first direction, the first sub-pixels and the third sub-pixels are arranged alternately to form a plurality of first sub-pixel rows, the second sub-pixels form a plurality of second sub-pixel rows, the first sub-pixel rows and the second sub-pixel rows are arranged alternately in a second direction, connection lines of center points of two first sub-pixels and two third sub-pixels form a first virtual quadrilateral, the two first sub-pixels are located at two vertex angles of the first virtual quadrilateral which are opposite to each other, one second sub-pixel is located within the first virtual quadrilateral, and the first virtual quadrilateral includes two interior angles each being equal to 90° and two interior angles each being not equal to 90°.

Abstract: An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective voltage supply line, connected to a first capacitor electrode and a semiconductor material layer. An orthographic projection of a first anode on a base substrate at least partially overlaps with an orthographic projection of a node connecting line in a respective first subpixel. An orthographic projection of a second anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective second subpixel. An orthographic projection of a third anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective third subpixel. An orthographic projection of a fourth anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective fourth subpixel.

Abstract: A display substrate, a method for manufacturing the same and a display device. In the display substrate, a sealant region includes: a corner sealant region, a lead-in sealant region, and a first sealant region on a first side of a display area. The corner sealant region is provided with an encapsulation base layer. A non-display area is provided with a second power line, a gate drive circuit and multiple first signal lines configured to provide signals to the gate drive circuit. The second power line includes a power line corner portion and a first power line portion, the first power line portion overlaps the first sealant region, and the first power line portion extends in a first direction. A target portion of each first signal line is at least located in the corner sealant region.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, a pixel defining layer and at least one photo spacer. The pixel defining layer is disposed on the base substrate and includes a plurality of openings, the at least one photo spacer is disposed on a side of the pixel defining layer away from the base substrate. A distance from any point at a bottom of the at least one photo spacer contacting the pixel defining layer to an upper edge of a side wall of the plurality of openings is greater than or equal to 5 ?m.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region which includes sub-pixels arranged in array, each sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extends in a first direction and include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row. A layer where the plurality of first reset signal lines are located is different from layers where the plurality of second reset signal lines are located.

Abstract: In the pixel circuit, the data writing-in circuit is configured to control to connect the data line and the second terminal of the driving circuit under the control of a first scanning signal provided by the first scanning line; the compensation control circuit is configured to control to connect the first terminal of the driving circuit and the connection node under the control of a second scanning signal provided by the second scanning line; the first control circuit is configured to control to connect the control terminal of the driving circuit and the connection node under the control of the first scanning signal.

Abstract: A display substrate and a display device. The display substrate includes a display region, a first connecting wire and a second connecting wire. The display region includes a first display region and a second display region. The first display region includes a plurality of light emitting devices arranged in an array, and the plurality of light emitting devices includes a first light emitting device and a second light emitting device. The second display region includes a plurality of first pixel circuit units, and the plurality of pixel circuit units includes a first pixel circuit and a second pixel circuit. The first connecting wire is connected to the first pixel circuit and the first light emitting device. The second connecting wire is connected to the second pixel circuit and the second light emitting device. The first direction and the second direction intersect each other.

Abstract: A pixel circuit and a driving method therefor, and a display panel. The pixel circuit includes a driving circuit, a data writing circuit, a compensation storage circuit, a first light-emitting control circuit and a second light-emitting control circuit. The driving circuit includes a control end, a first end, and a second end, and is configured to control a driving current which flows through the first end and the second end and which is used for driving a light-emitting element to emit light; the data writing circuit is connected to a first scanning signal line and is configured to, in response to a first scanning signal provided by the first scanning signal line, write a data signal into the first end of the driving circuit; the data writing circuit and the first light-emitting control circuit repel one another in a connected state under the control of the first scanning signal.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a display region; the display region includes a first display region and a second display region arranged in a second direction; each scanning signal line in the first display region is electrically connected with less pixels than each scanning signal line in the second display region; the first display region is divided into a first sub-display region and a second sub-display region arranged in the second direction; and the first sub-display region is located at the side far away from the second display region.

Abstract: A display substrate and a display device are provided. The display substrate includes a base and subpixels. The subpixel includes: a data line pattern; a power source signal line pattern including a portion extending in the first direction; and a subpixel driving circuitry. The subpixel driving circuitry includes two switching transistors, a driving transistor, and a storage capacitor. First and second electrode plates of the storage capacitor are coupled to a gate electrode of the driving transistor and the power source signal line pattern respectively. Second electrodes of the two switching transistors are coupled to a first electrode of the driving transistor. An orthogonal projection of the second electrode of at least one of the switching transistors onto the base at least partially overlaps an orthogonal projection of the power source signal line pattern onto the base, and at least partially overlaps an orthogonal projection of the second electrode plate of the storage capacitor onto the base.

Abstract: A display apparatus includes a display panel, a memory, and a driver. The memory stores at least one set of correspondences, and each set of correspondences includes 2N grayscale data and 2N register values in a one-to-one correspondence with the 2N grayscale data; each register value represents a grayscale voltage value of corresponding grayscale data; and N is a positive integer greater than or equal to 6. The driver obtains the at least one set of correspondences from the memory; receives image data from a signal transmission interface, the image data including a plurality of grayscale data corresponding to a plurality of sub-pixels; for any grayscale data in the image data, obtains a register value corresponding to the grayscale data in a set of correspondences; and outputs a grayscale voltage corresponding to a grayscale voltage value represented by the register value to the display panel according to the register value.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and includes a shift register unit, a first clock signal line, and a second clock signal line in a peripheral region; a first portion and a second portion of a first connection wire of the display substrate are connected to a first gate electrode of a first control transistor of the shift register unit; an orthographic projection of the first portion on the base substrate is on a side of an orthographic projection of an active layer of the first control transistor on the base substrate away from a display region; and an orthographic projection of the second portion on the base substrate is on a side of the orthographic projection of the active layer of the first control transistor on the base substrate close to the display region.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region; the first display region includes at least one first light emitting element, and the second display region includes at least one first pixel circuit; the first signal line includes a first main body portion and a first winding portion; the first main body portion extends along a first direction, and at least part of the first winding portion extends along a direction intersecting with the first direction; at least one first signal line is electrically connected to at least one first pixel circuit; and at least one first pixel circuit is configured to respectively drive at least one first light emitting element.

Abstract: The present disclosure provides a shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and an impedance transistor; the second transistor has a first electrode coupled to a second node; the third transistor has a first electrode coupled to a first power terminal and a second electrode coupled to the second node; the fifth transistor has a control electrode coupled to a third node; the impedance transistor has a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node.

Abstract: A display panel, a method for manufacturing the same and a display device are provided. In a second pixel region of the display panel, there is a first gap between first and second electrical connection elements in a first electrical connection layer, there is a second gap between third and fourth electrical connection elements in a second electrical connection layer, a third electrical connection layer is coupled to a fifth signal line pattern included in each sub-pixel of a corresponding sub-pixel group. The fifth signal line pattern is used to transmit a fifth signal with a fixed electrical potential, and an orthographic projection of the third electrical connection layer onto a substrate of the display panel covers at least part of an orthographic projection of the first gap onto the substrate and at least part of an orthographic projection of the second gap onto the substrate.

Abstract: A display substrate includes a first display region, a second display region, and a frame region. Light-emitting devices include first light-emitting devices in the first display region and second light-emitting devices in the second display region. Pixel drive circuits include first pixel drive circuits in the frame region and second pixel drive circuits in the second display region. The first pixel drive circuits are electrically connected to the first light-emitting devices. The second pixel drive circuits are electrically connected to the second light-emitting devices. Each of shift registers cascaded in the frame region is connected to the first pixel drive circuits and the second pixel drive circuits which are electrically connected to one row of first light-emitting devices and the same one row of second light-emitting devices respectively.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; and the second signal line group is on a side of the plurality of power lines and the first signal line group away from the pixel array region.