Abstract: To reduce the pre-programming cost, an efficient three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. It comprises a dummy word line and a plurality of dummy bit lines. Only the dummy OTP cells at the intersections of the dummy word line and dummy bit lines are programmed. All other dummy OTP cells are unprogrammed.

Abstract: The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

Abstract: The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

Abstract: The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.

Abstract: In a compact three-dimensional memory (3D-MC), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.

Abstract: To implement a complex math function, i.e. a math function with multiple input variables, a configurable computing array comprises at least an array of configurable computing elements. Each configurable computing element comprises at least a memory which stores a look-up table (LUT) for a math function with a single input variable.

Abstract: To reduce the pre-programming cost, an efficient three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. It comprises a dummy word line and a plurality of dummy bit lines. Only the dummy OTP cells at the intersections of the dummy word line and dummy bit lines are programmed. All other dummy OTP cells are unprogrammed.

Abstract: The present invention discloses a configurable computing array using two-sided integration. It is a monolithic integrated circuit comprising at least a configurable computing element located on one side of the substrate and at least a configurable logic element on the other side of the substrate. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.

Abstract: A multi-bit-per-cell three-dimensional read-only memory (3D-OTPMB) comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.

Abstract: The present invention discloses a configurable computing array. It comprises an array of configurable computing elements and an array of configurable logic elements. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.

Abstract: A preferred data storage with in-situ string-searching capabilities comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional vertical one-time-programmable memory (3D-OTPV) array vertically stacked above a pattern-processing circuit. The 3D-OTPV array stores at least a portion of big data. A search string from the input is sent to all SPUs, which perform string searching simultaneously.

Abstract: The present invention discloses a configurable computing array. It is a monolithic integrated circuit comprising at least a configurable computing element and a configurable logic element. The configurable computing element comprises at least a three-dimensional vertical writable memory (3D-WV) array, which is stacked above the configurable logic element and stores at least a portion of a look-up table (LUT) for a math function.

Abstract: To detect side-by-side parked vehicles at night, the present invention discloses a night-detection device and method. The night-detection device comprises a moving-vehicle sensor and a parked-vehicle sensor. It uses the light beam from a passing-by vehicle to extract at least a reflection of at least a head-light or at least a portion of a front bumper.

Abstract: The present invention discloses a three-dimensional vertical read-only memory (3D-OTPV) comprising Schottky diodes. It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. A plurality of Schottky diodes are formed between the horizontal address lines and the vertical address lines.

Abstract: The present invention discloses a configurable computing array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.

Abstract: The present invention discloses a configurable gate array comprising three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with in-situ string-searching capabilities (3D-MSS). It comprises a plurality of storage-processing units (SPU). Each SPU comprises at least a 3D-M array for storing computer data and a pattern-processing circuit for searching the computer data for a search string. The 3D-M array is stacked above the pattern-processing circuit. Multiple 3D-MSS dice can form a storage card or a solid-state drive with in-situ string-searching capabilities.

Abstract: The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTPV) comprising no separate diode layer. It comprises a plurality of vertically stacked horizontal address lines, at least a memory hole through the horizontal address lines, a memory layer and a vertical address line disposed in the memory hole. The memory layer comprises a re-programmable layer but no separate diode layer. The memory layer is leaky, i.e. its reverse current is comparable to its forward current. Sense amplifiers and a full-read mode are used to ensure a properly working 3D-MTPV.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with in-situ anti-malware capabilities (3D-MAM). It comprises a plurality of storage-processing units (SPU). Each SPU comprises at least a 3D-M array for storing computer data and a pattern-processing circuit for screening the computer data against a malware pattern. The 3D-M array is stacked above the pattern-processing circuit. Multiple 3D-MAM dice can form a storage card, or a solid-state drive with in-situ anti-malware capabilities.

Abstract: The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The horizontal address lines and the vertical address lines comprise oppositely-doped semiconductor materials.