Abstract: A read circuit for an image sensor includes: a first analog-to-digital conversion unit configured to perform successive approximation high-bit analog-to-digital conversion on collected pixel data to obtain high-bit conversion data and residual pixel data; and a second analog-to-digital conversion unit electrically connected to the first analog-to-digital conversion unit and configured to perform single-slope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data, wherein a sum of a first conversion accuracy of the first analog-to-digital conversion unit and a second conversion accuracy of the second analog-to-digital conversion unit is equal to a preset conversion accuracy for the pixel data. In accordance with the read circuit, a high image conversion frame rate of the pixel data can be achieved with lower power consumption and less circuit area, and the conversion cycle of the pixel data is effectively shortened.

Abstract: A pixel processing circuit, a reading method thereof and an image sensor are provided. The pixel processing circuit includes a pixel array comprising a plurality of pixel units arranged in a Bayer array, an Analog-to-Digital Converter (ADC) module comprising a plurality of analog-to-digital converters and a plurality of switch selection modules. The analog-to-digital converters are respectively located on the opposite first side and second side of the pixel array. The switch selection modules are set between the pixel array and the analog-to-digital converters to switch the connectivity between the pixel units and the analog-to-digital converters on the opposite sides of the pixel array so that signals of green pixel units are read by first analog-to-digital converters located at the first side of the pixel array, and signals of remaining color pixel units are read by second analog-to-digital converters that are located at the second side of the pixel array.

Abstract: A pixel processing circuit, a reading method thereof and an image sensor are provided. The pixel processing circuit includes a pixel array comprising a plurality of pixel units arranged in a Bayer array, an Analog-to-Digital Converter (ADC) module comprising a plurality of analog-to-digital converters and a plurality of switch selection modules. The analog-to-digital converters are respectively located on the opposite first side and second side of the pixel array. The switch selection modules are set between the pixel array and the analog-to-digital converters to switch the connectivity between the pixel units and the analog-to-digital converters on the opposite sides of the pixel array so that signals of green pixel units are read by first analog-to-digital converters located at the first side of the pixel array, and signals of remaining color pixel units are read by second analog-to-digital converters that are located at the second side of the pixel array.

Abstract: A read circuit for an image sensor includes: a first analog-to-digital conversion unit configured to perform successive approximation high-bit analog-to-digital conversion on collected pixel data to obtain high-bit conversion data and residual pixel data; and a second analog-to-digital conversion unit electrically connected to the first analog-to-digital conversion unit and configured to perform single-slope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data, wherein a sum of a first conversion accuracy of the first analog-to-digital conversion unit and a second conversion accuracy of the second analog-to-digital conversion unit is equal to a preset conversion accuracy for the pixel data. In accordance with the read circuit, a high image conversion frame rate of the pixel data can be achieved with lower power consumption and less circuit area, and the conversion cycle of the pixel data is effectively shortened.

Abstract: A method and a system for reducing column noise of an image sensor are provided. The method includes: reading dark pixel data in each image frame and reading initial effective pixel data in each image frame, where dark pixels and initial effective pixels are both arranged in N columns; sequentially calculating the dark pixel data to obtain an average value of each column of dark pixels and an entire average value of the dark pixels in each image frame; obtaining a corrected value of each column according to the average value of each column of dark pixels and the entire average value of the dark pixels; and calculating the corrected value of each column and the corresponding initial effective pixel data in each image frame to obtain target effective pixel data. In the method, the dark pixel data is pre-processed.

Abstract: The present invention discloses an image sensor for real-time calibration of dark current, including a pixel array comprises at least a pixel unit, the pixel unit includes a pixel photosensitive portion, a pixel dark shielding portion and a subtraction circuit, photodiodes in the pixel photosensitive portion and the pixel dark shielding portion are isolated by deep trench isolations, the pixel dark shielding portion are covered by a dark shielding layer; both of the pixel photosensitive portion and the pixel dark shielding portion adopt a same voltage and sequential control, a light ambient voltage signal and a non-light ambient voltage signal are generated and connected to both ends of a subtraction circuit to realize subtraction and dark current calibration.

Abstract: The present disclosure refers to a multispectral image sensor and a manufacturing method thereof. The multispectral image sensor comprises a front-end structure used for photoelectric conversion and processing, and a pixel layer provided on the front-end structure. The pixel layer comprises N pixel units, and N?4, the pixel units are arranged in a plurality of arrays, a photosensitive wavelength of each pixel unit in each array is different. Whereby, multispectrals can be detected simultaneously, and therefore the efficiency is improved, costs are reduced, and miniaturization is achieved.

Abstract: A MIPI D-PHY circuit comprises a main control module, a controlled module, an internal data source generating module, and a configuration register. The main control module and the controlled module are respectively connected to the configuration register, and the main control module is connected to the internal data source generating module. The main control module and the controlled module comprise a clock channel and a data channel respectively. The clock channel and the data channel in the main control module and the data channel and the clock channel in the controlled module both comprise an error detection unit. The MIPI D-PHY circuit provided by the present disclosure adopts the error detection unit to detect the signals of the main control module and the controlled module.

Abstract: The present invention discloses a motion detection circuit applied to CIS and a motion detection method.

Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Abstract: A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process.

Abstract: The present disclosure provides a FINFET device integrated with a TFET and its manufacturing method. Two end portions of the fin structure respectively form an N-type doped drain and a source which is consisted by a top P-type doped region and a bottom N-type doped region. As a result, the bottom N-type doped region of the source, the drain, the channel, the high-k dielectric layer and the gate structure on the surface of the sidewall of the fin structure form a MOS FINFET device, and the top P-type doped region of the source, the drain, the channel, the high-k dielectric layer and the gate structure on the top surface of the fin structure form the TFET device. The integration of the TFET and the FINFET is achieved, which decreases the cost.

Abstract: A full-frame image sensor system comprises at least a pair of readout circuits, at least a pair of channel selection circuits, and at least a pair of interface circuits arranged symmetrically with respect to a pixel array; the readout circuits are electrically connected to two sides of the pixel array respectively; the channel selection circuit and the readout circuit on a same side of the pixel array are electrically connected to each other. The interface circuit and the channel selection circuit on a same side of the pixel array are electrically connected to each other. As a result, the circuits on the two sides of the pixel array are substantially symmetrical, the center of the pixel array coincides with the center of the entire chip.

Abstract: A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate.

Abstract: The present invention discloses a test structure and a method for judging the de-embedding accuracy of RF devices, which comprises testing the S parameters of a target device test structure, an introduced device test structure and an auxiliary test structure, respectively. Then calculating de-embedding S parameters of the target device test structure and the introduced device test structure according to the above-tested results, respectively. Finally, calculating performance parameters of the target device test structure according to the above-calculated de-embedding S parameters. So, the accuracy of the de-embedding method is determined by comparing the consistency of the performance parameters. The present invention can directly judge the de-embedding accuracy and the applicable frequency range of a given de-embedding method by analyzing the testing data. Further, the using of the parallel test structure and the cascade test structure together can increase the reliability of the judgment results.

Abstract: A method and system for testing optimization and molding optimization of semiconductor devices. The testing optimization method is executed based on a test structure for testing the specific non-direct-current parameters, constructing an auxiliary structure of the test structure and testing the non-direct-current parameter, calculating the parallel parasitic resistance and the series parasitic resistance of the test structure based on the parasitic network model and the testing result of the auxiliary structure; performing linear fitting on the parallel parasitic resistance and the series parasitic resistance; and performing a direct-current testing on the test structure to obtain direct-current testing data and correcting the direct-current testing data based on the direct-current equivalent sub-circuit model.

Abstract: A median filter device is provided with a reordered circuit, a comparison circuit and a data refresh circuit on the basis of the conventional data buffer circuit and data register circuit. The reorder circuit re-sorts the signal data stored in the data buffer circuit in a preceding clock cycle according to their numerical values. The comparison circuit compares the new signal datum entered in the current clock cycle with the signal data already stored to generate a median. The data refresh circuit updates the signal codes stored in the data register circuit with the signal codes corresponding to the new signal data, for calculation of the median in a following clock cycle. The length of the data buffer circuit and data register circuit can be reduced from N signal data to N?1 signal data, which achieves less data storage capacity, smaller circuit area, easier data processing and higher operation efficiency.