Abstract: A non-volatile memory cell using two transistors, a bit select and a sense device and an antifuse device. The antifuse device is implemented with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and a current under 5-?A is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.

Abstract: A method and fixture using magnetic field assisted self-alignment for chip packaging. Typical embodiments include a magnetic device having one or more pole groups, each pole group including two or three poles. Some embodiments provide multiple pole groups arranged in a one or two dimensional pole group array. The poles can build up a self-alignment magnetic field. The structure of fixture is simple and easy to implement. Typical embodiments can greatly reduce chip packaging cost and make packaging more efficient. In accordance with typical embodiments, a chip and a substrate can be self-aligned magnetically regardless of their shapes.

Abstract: A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.