Abstract: Provided are a high-voltage blocking device (HVBD), a three-dimensional memory, and a preparation method thereof, relating to the technical field of three-dimensional memory manufacturing. The HVBD layer is provided with a plurality of vertical MOS through-holes; HVBDs are embedded in the HVBD layer through the corresponding vertical MOS through-holes; the HVBD layer includes a decoder array connection layer, a gate control layer, and a bit line connection layer that are sequentially arranged from bottom to top; the decoder array connection layer, the gate control layer, and the bit line connection layer are each provided with a plurality of MOS through-holes. This application, by embedding the HVBDs between a bit line decoder array and a three-dimensional stacked memory array, can reduce a planar area occupied by the three-dimensional memory while preventing electrical breakdown of a gate insulating layer of a bit line selection transistor.

Abstract: A method for manufacturing a high-density three-dimensional programmable memory, relating to the memory manufacturing technology, comprises the following steps: 1) forming a base structure; 2) grooving the base structure; 3) disposing, storage medium layers required by a preset memory structure layer by layer on an inner wall of the division groove; 4) filling a core medium in the division groove to form a core medium layer; 5) etching, through a mask etching process, to form deep holes along the separation division groove filled with the core where the deep holes truncate the core medium in the division groove; and 6) filling an insulation medium in the deep holes. The method has the beneficial effects of low costs and the highest storage density.

Abstract: A fabrication method of three-dimensional programmable memory includes: 1) forming a base structure; 2) trenching the base structure; 3) setting the preset memory structure layer by layer onto the inner wall of strip trench; 4) filling the core medium in the cavity of the strip trench to form core medium layer; 5) setting the isolation trenches and isolation trench holes to isolate the left-right fingers and memory units, respectively, where the isolation trenches encroach at least one memory medium layer at the strip trench, and form a curve by connecting with the strip trenches from end to end. The isolation holes are set at the strip trenches to divide the strip into at least three independent memory bodies and encroach the medium layers of the base structure near the long sides of the strip trenches; and 6) filling the isolation trenches and holes with insulating medium.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a fabrication method, and relates to the preparation technology of memories. The memory comprises an underlying circuit part and a basic structure body disposed above the underlying circuit part, wherein the basic structure body is divided into two independent interdigitated structures by a curve-shaped division groove, at least three memory cell holes are formed in the curve-shaped division groove side by side, a vertical electrode is disposed in each memory cell hole, and the memory medium is an insulating medium; and a buffer region is placed on the inner wall of the memory cell hole and at the position of a first conducting medium layer, the buffer region protrudes from the inner wall of the memory cell hole to the central axis of the memory cell hole, and the buffer region is connected to the memory medium.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a preparation method. The preparation method of the memory comprises the following steps: firstly forming a basic structure body; secondly, slotting the basic structure body; thirdly, forming a preset number of memory cell holes in the a segmentation groove, an insulating medium being arranged between every two adjacent memory cell holes, a vertical electrode being arranged in the memory cell hole, and a memory medium layer being arranged between the vertical electrode and an interdigital structure; and in the third step, before the memory medium is arranged, the preparation method comprises the following steps: performing doping diffusion on the first conducting medium located on the inner wall of the segmentation groove, so that the first conducting medium close to the inner wall of the segmentation groove forms a buffer area made of a low-doped semiconductor material.

Abstract: Provided are an underlying transistor circuit of a semiconductor memory and a preparation method for the same. The circuit includes a row line layer, a column line layer positioned above the row line layer, and an insulating isolation layer between the row line layer and the column line layer, with directions of the row lines and the column lines being perpendicular to each other. Holes penetrating the column line layer and the insulating isolation layer are provided at intersections of row lines and column lines; upper and lower segments of the hole are both filled with semiconductor materials; the semiconductor material in the upper segment of the hole has a doping type the same as that of the row line, while the semiconductor material in the lower segment of the hole has a doping type opposite to that of the row line, thus, a transistor is formed in each hole.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a fabrication method, and relates to the preparation technology of memories. The memory comprises an underlying circuit part and a basic structure body disposed above the underlying circuit part, wherein the basic structure body is divided into two independent interdigitated structures by a curve-shaped division groove, at least three memory cell holes are formed in the curve-shaped division groove side by side, a vertical electrode is disposed in each memory cell hole, and the memory medium is an insulating medium; and a buffer region is placed on the inner wall of the memory cell hole and at the position of a first conducting medium layer, the buffer region protrudes from the inner wall of the memory cell hole to the central axis of the memory cell hole, and the buffer region is connected to the memory medium.

Abstract: The present disclosure provides a method for manufacturing a fully self-aligned high-density 3D multi-layer memory, which relates to the technical field of memory manufacturing. The method includes the following steps: 1) forming a base structure; 2) grooving the base structure; 3) filling an insulating medium in the division groove; 4) deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, where the insulating medium is present between adjacent memory cell holes, and conductive medium layers and insulating medium layers of the base structure are exposed in the memory cell holes; and 5) disposing various layers of medium required by a preset memory structure layer by layer onto the inner walls of the memory cell holes. The semiconductor memory manufactured according to the present disclosure has high storage density.

Abstract: Disclosed are an interconnection structure of a high-density three-dimensional (3D)-stacked memory and preparation method for same, relating to integrated circuit technologies, and in particular, to three-dimensional semiconductor memory technologies. According to the present disclosure, the interconnection structure of a high-density 3D-stacked memory includes a three-dimensional storage structure, which is formed by alternately stacked conductive layers and insulating layers, and a lead-out structure. A contact surface between the lead-out structure and an etching facade of the three-dimensional storage structure has a stepped edge line, and the etching facade is a plane of a side surface of the three-dimensional storage structure, which is generated due to etching and perpendicular to a bottom surface.

Abstract: Provided are an underlying transistor circuit of a semiconductor memory and a preparation method for the same, which relate to the integrated circuit technologies. The circuit of the present disclosure includes a row line layer, a column line layer positioned above the row line layer, and an insulating isolation layer between the row line layer and the column line layer, with directions of the row lines and the column lines being perpendicular to each other. Holes penetrating the column line layer and the insulating isolation layer are provided at intersections of row lines and column lines; upper and lower segments of the hole are both filled with semiconductor materials; the semiconductor material in the upper segment of the hole has a doping type the same as that of the row line, while the semiconductor material in the lower segment of the hole has a doping type opposite to that of the row line, thus, a transistor is formed in each hole.

Abstract: Provided are a semiconductor memory underlying circuit and a preparation method for the same. The semiconductor memory underlying circuit of the present disclosure includes a row line layer, a column line layer located above the row line layer, and an insulating isolation layer between the row line layer and the column line layer. A predetermined number of row lines made of a doped semiconductor material are provided inside the row line layer, and a predetermined number of column lines made of a conductive material are provided inside the column line layer, with directions of the row lines and the column lines being perpendicular to each other. Metal oxide semiconductor (MOS) holes penetrating the column line layer and the insulating isolation layer are provided at intersections of the row lines and column lines. An upper segment and a lower segment of the MOS hole both are filled with conductive materials.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a preparation method. The preparation method of the memory comprises the following steps: firstly forming a basic structure body; secondly, slotting the basic structure body; thirdly, forming a preset number of memory cell holes in the a segmentation groove, an insulating medium being arranged between every two adjacent memory cell holes, a vertical electrode being arranged in the memory cell hole, and a memory medium layer being arranged between the vertical electrode and an interdigital structure; and in the third step, before the memory medium is arranged, the preparation method comprises the following steps: performing doping diffusion on the first conducting medium located on the inner wall of the segmentation groove, so that the first conducting medium close to the inner wall of the segmentation groove forms a buffer area made of a low-doped semiconductor material.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a fabrication method, and relates to the preparation technology of memories. The memory comprises an underlying circuit part and a basic structure body disposed above the underlying circuit part, wherein the basic structure body is divided into two independent interdigitated structures by a curve-shaped division groove, at least three memory cell holes are formed in the curve-shaped division groove side by side, a vertical electrode is disposed in each memory cell hole, and the memory medium is an insulating medium; and a buffer region is placed on the inner wall of the memory cell hole and at the position of a first conducting medium layer, the buffer region protrudes from the inner wall of the memory cell hole to the central axis of the memory cell hole, and the buffer region is connected to the memory medium.

Abstract: A fabrication method of three-dimensional programmable memory includes: 1) forming a base structure; 2) trenching the base structure; 3) setting the preset memory structure layer by layer onto the inner wall of strip trench; 4) filling the core medium in the cavity of the strip trench to form core medium layer; 5) setting the isolation trenches and isolation trench holes to isolate the left-right fingers and memory units, respectively, where the isolation trenches encroach at least one memory medium layer at the strip trench, and form a curve by connecting with the strip trenches from end to end. The isolation holes are set at the strip trenches to divide the strip into at least three independent memory bodies and encroach the medium layers of the base structure near the long sides of the strip trenches; and 6) filling the isolation trenches and holes with insulating medium.