Abstract: A high-speed high-linearity time-interleaved dynamic operational amplifier circuit includes a first current channel and a second current channel. The first current channel includes a first MOS transistor, a second MOS transistor and a third MOS transistor which are sequentially connected in series between a high level and a ground level. The first MOS transistor and the second MOS transistor have opposite conductivity types. A control end of the first MOS transistor is connected to a control end of the second MOS transistor. The second current channel includes a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor which are sequentially connected in series between the high level and the ground level. The fourth MOS transistor and the fifth MOS transistor have opposite conductivity types. A control end of the fourth MOS transistor is connected to a control end of the fifth MOS transistor.

Abstract: A high-linearity dynamic amplifier includes a first differential branch and a second differential branch. The first differential branch includes a first MOS transistor and a second MOS transistor which are connected between a high-level terminal and a ground-level terminal in series. A connection point of the first MOS transistor and the second MOS transistor is a second output terminal. The second differential branch includes a third MOS transistor and a fourth MOS transistor which are connected between the high-level terminal and the ground-level terminal in series. A connection point of the third MOS transistor and the fourth MOS transistor is a first output terminal. A grid terminal of the second MOS transistor is connected to a drain terminal of the fourth MOS transistor. A grid terminal of the fourth MOS transistor is connected to a drain terminal of the second MOS transistor.

Abstract: A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.

Abstract: A data transmission circuit includes a data sending module and a data receiving module. The data sending module includes a message identification unit, used for sending messages to corresponding encapsulation units according to a priority of message data to be sent; a low-priority message encapsulation unit, used for slicing low-priority messages, encapsulating message slices respectively to form low-priority message slice packets, and then sending the low-priority message slice packets to a low-priority sending queue; a high-priority message encapsulation unit, used for encapsulating high-priority messages to form high-priority message packets and then sending the high-priority message packets to a high-priority sending queue; and a message sending unit, used for sending message packets in the high-priority sending queue and the low-priority sending queue, and preferentially processing the high-priority sending queue.

Abstract: A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.

Abstract: A high-speed high-linearity time-interleaved dynamic operational amplifier circuit includes a first current channel and a second current channel. The first current channel includes a first MOS transistor, a second MOS transistor and a third MOS transistor which are sequentially connected in series between a high level and a ground level. The first MOS transistor and the second MOS transistor have opposite conductivity types. A control end of the first MOS transistor is connected to a control end of the second MOS transistor. The second current channel includes a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor which are sequentially connected in series between the high level and the ground level. The fourth MOS transistor and the fifth MOS transistor have opposite conductivity types. A control end of the fourth MOS transistor is connected to a control end of the fifth MOS transistor.