Patents Assigned to China Wafer Level CSP Co., Ltd.
  • Publication number: 20190189675
    Abstract: A chip packaging method and a chip package are provided. According to the chip packaging method and the chip package, to-be-packaged chips are located in a plastic packaging layer, and front surfaces of the to-be-packaged chips are flush with a first surface of the plastic packaging layer, and the plastic packaging material for manufacturing the plastic packaging layer has good plasticity before a curing process, so that the formed first surface and the second surface have good smoothness, thereby ensuring the reliability of the package.
    Type: Application
    Filed: August 21, 2018
    Publication date: June 20, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventor: Zhiqi Wang
  • Publication number: 20190189578
    Abstract: A fingerprint chip packaging method and a fingerprint chip package are provided. During a process of packaging a fingerprint chip, the fingerprint chip is directly packaged and protected by a mold compound layer to form a thin package. With the fingerprint chip packaging method and the fingerprint chip package, the thickness of the package is greatly reduced, which facilitates miniaturization of the electronic device. Further, since the mold compound layer formed after curing of a mold compound material has a great mechanical strength, the mold compound layer can serve as a carrier substrate for mounting other electronic components of the electronic device, such that the integration of the electronic device is greatly improved, the space of the circuit board is saved, thereby facilitating the miniaturization of the electronic device.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 20, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventor: Zhiqi Wang
  • Publication number: 20190188447
    Abstract: An optical fingerprint recognition chip package and a packaging method are provided. In the optical fingerprint recognition chip package, a cover plate is arranged on a front surface of an optical fingerprint recognition chip, the cover plate includes a substrate and a light shielding layer. The light shielding layer is arranged on a surface of the substrate facing away from the optical fingerprint recognition chip. The substrate is provided with multiple first through holes for exposing photosensitive pixels of the optical fingerprint recognition chip. The light shielding layer is provided with multiple second through holes in one-to-one correspondence with the first through holes. During fingerprint recognition, light reflected by a finger is split through the first through holes and the second through holes, such that crosstalk among different photosensitive pixels is reduced, and the accuracy of fingerprint recognition is improved.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 20, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
  • Patent number: 10325946
    Abstract: A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 18, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
  • Publication number: 20190165028
    Abstract: A package-on-package structure of an image sensing chip is provided, which includes: an image sensing chip package, a control chip package and a circuit board. The image sensing chip package and the control chip package are arranged on the same surface of the control chip package in parallel. The image sensing chip package includes a first substrate and an image sensing chip. The control chip package includes a second substrate and a control chip. A second surface of the first substrate is electrically connected to a first region of a first surface of the second substrate, and the circuit board is electrically connected to a second region of the first surface of the second substrate. A package-on-package method for a package-on-package structure is further provided.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 30, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventor: Zhiqi Wang
  • Publication number: 20190165030
    Abstract: An image sensing chip package and an image sensing chip packaging method are provided. In the image sensing chip package, an image sensing chip is located in a through hole of a substrate, and a front surface of the image sensing chip is flush with a first surface of the substrate. In this way, in the image sensing chip package, a height of the image sensing chip is controlled with the first surface of the substrate as a reference. Since the first surface of the substrate does not change in the packaging process, almost no uncontrollable factor affects the height of the image sensing chip.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 30, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventor: Zhiqi Wang
  • Publication number: 20190165013
    Abstract: A package for an iris recognition imaging module and a method for manufacturing a package for an iris recognition imaging module are provided. An image sensing chip is bonded with a substrate having a window, with an image sensing region of the image sensing chip being facing towards the window and covered by the window. The image sensing chip is electrically connected with a wiring line. The substrate is provided with an infrared light-emitting diode (LED), and a shielding member for preventing at least a part of infrared light emitted by the infrared LED from entering the image sensing region. With the shielding member, the amount of infrared light of the infrared LED entering the image sensing chip can be reduced while providing compensation light, thereby reducing interference to the iris imaging and improving the accuracy of the iris recognition.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Mingxuan Wu
  • Patent number: 10283483
    Abstract: A packaging method and package structure for an image sensing chip are provided. The method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each having an image sensing region and contact pads arranged on a side of the first surface of the wafer; forming openings extending towards the first surface on the second surface of the wafer, to expose the contact pads; forming V-shaped cutting trenches extending towards the first surface on the second surface of the wafer; and applying a photosensitive ink on the second surface of the wafer, to completely fill the V-shaped cutting trenches, cover the openings, and form a hollow cavity between each of the openings and the photosensitive ink.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 7, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
  • Patent number: 10276540
    Abstract: A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a fist surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 30, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Ying Yang, Wei Wang
  • Publication number: 20190074258
    Abstract: A solder pad, a semiconductor chip including the solder pad, and a forming method therefor are provided. A solder pad includes at least two metal layers and a dielectric layer located between adjacent metal layers. The solder pad includes a laser drilling region; the dielectric layer is provided with an opening corresponding to the laser drilling region; a metal plug is provided in the opening, both ends of the metal plug being respectively in contact with the adjacent metal layers. A method for forming a solder pad improves the quality of laser drilling performed on a solder pad and reduces the difficulty of the laser drilling; laser acts on a metal substance without being in contact with a dielectric layer, so as to effectively prevent a dielectric layer from heat distortion.
    Type: Application
    Filed: October 14, 2016
    Publication date: March 7, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Xinqin Wang
  • Publication number: 20190074309
    Abstract: A package for an image sensing chip is provided, which includes: an image sensing chip comprising a first surface and a second surface opposite to each other, where the first surface is provided with an image sensing region and a contact pad; a through hole extending from the second surface to the contact pad; an electrical connection layer provided along an inner wall of the through hole and extending onto the second surface; a solder mask filling the through hole and covering the electrical connection layer, wherein an opening is formed in the solder mask, and the electrical connection layer is exposed at a bottom of the opening; a guide contact pad covering an inner wall and the bottom of the opening and extending onto the solder mask; and a solder bump located on the guide contact pad.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 7, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
  • Publication number: 20190067352
    Abstract: An image sensor chip package and a packaging method thereof are provided. The image sensor chip package includes: an image sensor chip having a first surface and a second surface opposite to each other, a photosensitive region being arranged on the first surface; a protective cover plate having a third surface and a fourth surface opposite to each other, the third surface covering the first surface; and a light shielding layer arranged on the fourth surface of the protective cover plate, the light shielding layer having an opening, and the photosensitive region being exposed through the opening. The light shielding layer includes a light absorbing layer located on the fourth surface and a metal layer located on the light absorbing layer.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 28, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Guoliang Xie
  • Publication number: 20190013302
    Abstract: A packaging method and a package structure for a fingerprint recognition chip and a drive chip are provided. The packaging method is a wafer-level packaging method. According to the method, a blind hole is formed on the back surface of a wafer and the drive chip is secured in the blind hole, then the wafer is cut to obtain a package structure for the fingerprint recognition chip and the drive chip. In this way, the drive chip is packaged in the back surface of the wafer-level fingerprint recognition chip, thereby reducing the complexity of the package process. In addition, the size of the package structure is close to the size of the single fingerprint recognition chip, thereby greatly reducing the size of the package structure and improving the integration of the package structure.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 10, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
  • Publication number: 20190010046
    Abstract: A packaging structure integrated with an MEMS chip and an ASIC chip and a packing method are provided. The packaging structure includes: an MEMS chip, an ASIC chip, a first solder bump and a cover plate. The MEMS chip has a front surface and an opposite back surface. The ASIC chip has a front surface and an opposite back surface. The front surface of the ASIC chip is laminated and fixed to the back surface of the MEMS chip, and the ASIC chip is electrically connected to the MEMS chip. The first solder bump is arranged on a side of the ASIC chip facing away from the MEMS chip, and electrically connects to an external circuit. The cover plate includes an accommodating cavity. The MEMS chip is located in the accommodating cavity and the cover plate is hermetically connected to the ASIC chip.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 10, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventor: Zhiqi Wang
  • Publication number: 20190006404
    Abstract: A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate structure, where a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit, the upper cover plate structure further includes a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.
    Type: Application
    Filed: August 5, 2016
    Publication date: January 3, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Fangyuan Hong
  • Publication number: 20190006253
    Abstract: A semiconductor chip package and a semiconductor chip packaging method are provided. The package includes: a semiconductor chip having a functional region, a protective substrate located on one side of the semiconductor chip and covering the functional region, and a support unit located between the protective substrate and the semiconductor chip and enclosing the functional region. The support unit includes an outer support member and an inner support member located inside the outer support member. A receiving cavity is formed between the inner support member, the semiconductor chip and the protective substrate. A hollow cavity is formed between the inner support member, the outer support member, the semiconductor chip and the protective substrate. The inner support member is provided with at least one first ventilating structure, through which the receiving cavity is in communication with the hollow cavity.
    Type: Application
    Filed: August 16, 2016
    Publication date: January 3, 2019
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Xianglong Liu, Yuanhao Xu
  • Publication number: 20180366387
    Abstract: A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.
    Type: Application
    Filed: April 11, 2018
    Publication date: December 20, 2018
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
  • Publication number: 20180337206
    Abstract: A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; an upper cover plate, where a first surface of the upper cover plate is provided with a support structure, the upper cover plate covers the first surface of the chip unit, the support structure is located between the upper cover plate and the chip unit, and the sensing region is located in a cavity enclosed by the support structure and the first surface of the chip unit; and a light shielding layer covering a second surface of the upper cover plate opposite to the first surface of the upper cover plate, where a central region of the second surface which overlaps with the sensing region in a light-transmission direction is exposed through the light shielding layer.
    Type: Application
    Filed: August 30, 2016
    Publication date: November 22, 2018
    Applicant: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Fangyuan Hong
  • Patent number: 10133907
    Abstract: A fingerprint recognition chip packaging structure and a packaging method. The packaging structure includes: a substrate provided with a substrate surface; a sensor chip coupled on the surface of the substrate, where the sensor chip is provided with a first surface and a second surface opposite the first surface, the first surface of the sensor chip is provided with a sensing area, and the second surface of the sensor chip is arranged on the surface of the substrate; a capping layer arranged on the surface of the sensing area of the sensor chip, where the material of the capping layer is a polymer; and, a lamination layer arranged on the surface of the substrate and that of the sensor chip, where the lamination layer exposes the capping layer. The packaging structure allows for reduced requirements on the sensitivity of the sensor chip, thus broadening applications.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 20, 2018
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Qiong Yu, Wei Wang
  • Patent number: 10126151
    Abstract: A chip package structure and packaging method are provided. The chip package structure includes a sensing chip, a covering layer located on the first surface of the sensing chip, and a plug structure located in the sensing chip. The sensing chip includes a first surface, a second surface opposite to the first surface, and a sensing area located on the first surface. The second surface of the sensing chip faces to a base plate. One end of the plug structure is electrically connected to the sensing area, and the other end of the plug structure is exposed by the second surface of the sensing chip.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 13, 2018
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Qiong Yu, Wei Wang