Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.

Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.

Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.

Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.

Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.

Abstract: The invention provides a Wafer Level Chip Size Packaging (WLCSP) target and a method for forming it. A WLCSP target is formed by recombining single chips, wafer parts each including two or more chips or half finished packaging targets which have been subjected to at least one previous step of packaging onto a first substrate, or bonding a wafer part which is formed by dicing a whole wafer and includes at least two chips to a second substrate for bonding. Thus, a wafer with a larger size can be packaged through the WLCSP on a WLCSP apparatus with a smaller size while benefiting from the advantages of the WLCSP, the WLCSP apparatus remains applicable within a longer period of time, the cost is lowered, and enterprises may keep up with the development of the market and the increase of the wafer size without having to update the WLCSP apparatus substantially.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.

Abstract: The present invention relates to an optical converter and a manufacturing method thereof and a light emitting diode. An optical converter for a light emitting diode includes two substrates, in which, a annular first cavity wall is arranged between the two substrates, and an airtight space filled with an optical conversion substance is surrounded by the first cavity wall and the two substrates. The invention implements the encapsulation and manufacturing of the optical conversion substance for the LED. The structure and the manufacturing method according to the invention can be utilized to encapsulate an active optical conversion substance in the optical converter while avoiding the active optical conversion substance reacting to other active substance, e.g., oxygen, during manufacturing. Furthermore, the optical conversion substance is encapsulated with wafer level chip size packaging to thereby improve the efficiency of manufacturing the optical converter and reduce the cost.

Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.

Abstract: The invention provides a Wafer Level Chip Size Packaging (WLCSP) target and a method for forming it. A WLCSP target is formed by recombining single chips, wafer parts each including two or more chips or half finished packaging targets which have been subjected to at least one previous step of packaging onto a first substrate, or bonding a wafer part which is formed by dicing a whole wafer and includes at least two chips to a second substrate for bonding. Thus, a wafer with a larger size can be packaged through the WLCSP on a WLCSP apparatus with a smaller size while benefiting from the advantages of the WLCSP, the WLCSP apparatus remains applicable within a longer period of time, the cost is lowered, and enterprises may keep up with the development of the market and the increase of the wafer size without having to update the WLCSP apparatus substantially.

Abstract: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

Abstract: The present invention provides patterned leads for a wafer level chip size package and methods for fabricating the same. The patterned leads include connection leads and solder pads. In designing, a compensation pattern is disposed on the connection lead or on the solder pad, so as to increase the distance between the connection lead and the solder pad. The present invention meets a tendency of increasing quantity per area of peripheral arrayed compatible pads and solder bumps on a semiconductor chip, and also saves more space for layout of leads on the chip bottom surface so as to avoid potential short circuit in between which happens in increasing probability with increasing quantity per area on the condition of the lead and the solder bump.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

Abstract: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.