Abstract: The present invention provides a self-timed differential amplifier, including an amplifier unit, having a pair of read/write terminals, wherein data is read or written by a select line; a pair of precharge transistors, controlled by a control line; and a pair of cross-coupled transistors, controlled by a column select line. Moreover, a complementary differential amplifier is formed by the combination of the pair of precharge transistors and the pair of cross-coupled transistors. The pair of the precharge transistors and the pair of cross-coupled transistors are connected to the pair of read/write terminals of the amplifier unit.

Abstract: A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell.

Abstract: A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell.

Abstract: A method for operating a non-volatile flash memory with a write protection mechanism is provided. The method comprises the steps as follow. A command is issued. When the command is a safeguard information modification command, only when the safeguard information modification command matches the specific combination of the plurality of modification instructions, a safeguard information is allowed to be modified. When the command is a flash memory data modification command, only when both the status register protection information and the safeguard information indicate that the memory block/sector is not under write-protection, the memory block/sector is allowed to be modified according to the flash memory data modification command.

Abstract: A two-transistor PMOS memory cell has a selective gate (SG) PMOS and a floating gate (FG) PMOS is provided. A control gate, overlapping the floating gate of the FG PMOS, of the memory cell is made by a polysilicon layer and located on an isolation structure.

Abstract: In a p-type flash memory array, separate programming and read bit lines are provided. The programming bit line is used only to program the floating gate transistors in the memory cells connected to that bit line. The read bit line is used only to read the state of a floating gate transistor in a selected memory cell connected to that bit line during the operation of the memory circuit. The resulting structure allows the use of low voltages during both programming and operation of the memory array. This makes possible the use of transistors in the memory array with feature sizes less than, for example, 0.18 microns. At the same time variable, unpredictable capacitances associated with each bit line in prior art p-type flash memory structures using comparable low programming voltages are eliminated when a particular memory cell attached to that bit line is being read out.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: A memory apparatus includes a main memory, a redundant memory, and a substitution control unit. The main memory is configured to receive a read address and output a main data word comprising a plurality of main data sub-words where the read address includes a first portion and a second portion. The redundant memory is configured to receive the read address first portion and output a redundant data sub-word. The substitution control unit includes a substitution control word memory configured to store a plurality of substitution control words and configured to receive the read address first portion and assert a substitution control word including a substitution address second portion. The read address first portion and substitution address second portion form a substitution address. The substitution control unit asserts a substitution control signal when there is a match between the read address and the substitution address.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.