Patents Assigned to Chip Engines
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Patent number: 9859871Abstract: Techniques describe tuning a plurality of radio stations, buffering digital audio data from each tuner, recognizing programming segments in the buffer, identifying content (e.g., song title and artist) of at least some segments, selecting from among the identified segments, and providing the selected segments to a listener. In an example, at least two signals are simultaneously tuned from at least two radio stations. Digital audio data and metadata obtained from the tuning may be buffered. The buffered data may be segmented into programming segments. Information may be obtained about the programming segments. For example, a song title and artist may be obtained for a programming segment comprising a song. In another example, a second programming segment may be identified as a commercial or may remain unidentified. The obtained information identifying programming segments may be analyzed to identify listener-preferred programming segments. Preferred programming segments may then be provided to the listener.Type: GrantFiled: March 19, 2015Date of Patent: January 2, 2018Assignee: Chip Engine, LLCInventors: David S. Thompson, David A. Divine
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Publication number: 20030177258Abstract: A method and system for adaptive multi-protocol resilient packet ring (RPR) processing are provided. The present invention provides optimal handling operations targeted for both legacy and evolving RPR functions related to topology discovery, fairness algorithms, and control-packet manipulation. Further, the present invention utilizes out-band paths, unique data and instruction memory constructs, and pipeline and multi-thread features to provide wire-rate performance. In one embodiment, a system of the present invention includes instruction memory; a fetch unit associated with instruction memory; a decode unit associated with the fetch unit; at least one execution unit associated with the decode unit; a load/store unit associated with the at least one execution unit; and data memory associated with the load/store unit.Type: ApplicationFiled: January 15, 2003Publication date: September 18, 2003Applicant: Chip EnginesInventors: Paritosh Kulkarni, Roxanna Ganji, Nirmal Raj Saxena
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Publication number: 20030118022Abstract: The present invention addresses the need for improved network data handling with a flexible, single point solution for packet header processing of data packets in a variable format transfer environment without associated performance or rate degradation. The present invention introduces a programmable or reconfigurable data packet header processor, wherein various registers (50, 55 and 60) of a chip are selectively programmed with a set of values that map the length (48) and location (44) of various header fields (20, 23, 25) to their position measured from the start of the packet (29). Unlike dedicated hardware solutions, these updateable registers are designed to store length (48), position (44) and type (40) data relating to multiple packet formats to improve extraction of packet header information by guiding the extraction to the exact point of the desired field information.Type: ApplicationFiled: December 20, 2002Publication date: June 26, 2003Applicant: Chip EnginesInventors: Paritosh Kulkarni, Nirmal Raj Saxena
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Publication number: 20030112816Abstract: The present invention provides a unique system and method for optimizing packet processing flow in a communications network by minimizing latency associated with packet-forwarding eligibility determinations. The present invention employs a speculative scheme with automatic recovery, including a two-way multithreaded implementation designed to overcome the aforementioned latency issue, including the functionality of enqueuing an incoming packet in both packet memory and a cut through buffer; determining the packet's eligibility for cutting through the buffer; and based on the determination, rolling back the unsuccessful process.Type: ApplicationFiled: December 19, 2002Publication date: June 19, 2003Applicant: Chip EnginesInventors: Prasad Modali, Anil Babu Nangunoori, Nirmal Raj Saxena
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Publication number: 20030112814Abstract: A system and method is provided for traffic management and regulation in a packet-based communication network, the system and method facilitating proactive, discriminating congestion control on a per flow basis of packets traversing the Internet via use of a Weighted Random Early Detection (WRED) algorithm that monitors the incoming packet queue and optimizes enqueuing or discard of incoming packets to stabilize queue length and promote efficient packet processing. During optimized discard conditions, the system and method discern a relative priority among incoming packets, distribute packets with a relatively high priority and discard packets with a relatively low priority. Additionally, packet traffic are policed and discarded according to packet type, quantity or other predetermined criteria. The present invention performs in periodic mode, demand mode or both, and can be implemented as a hardware solution, a software solution, or a combination thereof.Type: ApplicationFiled: December 13, 2002Publication date: June 19, 2003Applicant: Chip EnginesInventors: Prasad Modali, Nirmal Raj Saxena