Patents Assigned to CHIP SOLUTIONS, LLC
-
Patent number: 10586746Abstract: Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.Type: GrantFiled: September 15, 2017Date of Patent: March 10, 2020Assignee: Chip Solutions, LLCInventor: Sukianto Rusli
-
Patent number: 10354907Abstract: A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source.Type: GrantFiled: May 11, 2018Date of Patent: July 16, 2019Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Patent number: 10332775Abstract: Disclosed herein is a releasable carrier that includes a supporting carrier, a carrier conductive layer, and a releasable tape located between the supporting carrier and the carrier conductive layer. The releasable tape attaches the supporting carrier to the carrier conductive layer. The releasable tape is configured to release the supporting carrier from the carrier conductive layer after being exposed to an activating source. The releasable carrier further includes a thin conductive layer attached to the carrier conductive layer, the thin conductive layer creating a surface configured to receive a conductive circuit. Further disclosed is a method for fabricating the releasable carrier and a method for making a semiconductor device using the releasable carrier.Type: GrantFiled: July 15, 2016Date of Patent: June 25, 2019Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Patent number: 9941146Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die is attached to the second surface. The substrate includes a layer of insulative material and at least a portion of an embedded conductive circuit in the layer of insulative material. The substrate includes an etched layer of a conductive material attached to the portion of the conductive circuit, the etched layer of the conductive material located on the first surface of the substrate.Type: GrantFiled: July 15, 2016Date of Patent: April 10, 2018Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Patent number: 9922949Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes a metal barrier layer plated onto a functional copper layer etched to form the conductive circuit. The conductive circuit has a thickness of less than or equal to 3 ?m. Further disclosed is a method of making a semiconductor device.Type: GrantFiled: January 13, 2017Date of Patent: March 20, 2018Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Patent number: 9847244Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed.Type: GrantFiled: July 15, 2016Date of Patent: December 19, 2017Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli
-
Patent number: 9812347Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed.Type: GrantFiled: July 15, 2016Date of Patent: November 7, 2017Assignee: CHIP SOLUTIONS, LLCInventor: Sukianto Rusli