Abstract: The present invention provides a programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof. In an embodiment, the programmable modular circuit comprises a plurality of serial-to-parallel interface registers coupled together by a data line, a clock line, and an enable line. Each of the plurality of serial-to-parallel interface registers is coupled to a module of the system-on-a-chip. The data line and the clock line are used to serially clock data into the plurality of serial-to-parallel interface registers. Applying a first logical value to the enable line provides the data serially clocked into the plurality of serial-to-parallel interface registers to modules of the system-on-a-chip. Applying a second logical value to the enable line provides default values to modules of the system-on-a-chip.

Abstract: The present invention discloses a calibration circuit for a voltage-controlled oscillator (10a-10c) and also a method for calibrating the voltage-controlled oscillator. The apparatus comprises a first counter (210) for counting the number of cycles of a reference signal (Fclk) and a second counter (220) for counting the number of cycles of a feedback signal (Fin) produced by the voltage-controlled oscillator (10a-10c). The second counter (220) is further adapted to produce a difference value (OUTVAL) representative of the difference between the phase of the reference signal (Fclk) and the phase of the feedback signal (Fin). A memory (240) has a plurality of memory locations storing the difference values (OUTVAL) and capacitor selections. The apparatus further comprises a capacitor bank (90) selectable by the capacitor selections in the memory (240) and connected to the voltage-controlled oscillator (10a-10c).

Abstract: The present invention provides a high definition media interface (HDMI) controller having a modular design internal bus structure, and applications thereof. The controller includes a circuit interface, an address decoder coupled to the circuit interface, a plurality of sub-circuits, wherein each sub-circuit includes registers used to configure and control the sub-circuit, and a bus that couples the registers of each sub-circuit to the address decoder. After startup of the controller, the sub-circuits are configured by using the circuit interface, address decoder, and bus to write values to the registers of the sub-circuits. The sub-circuits of the controller include a video pixel sampler, an audio sampler, a frame composer, and a power controller. The video sampler can be configured to convert one of a plurality of RGB and YCbCr signals to a common format signal used by other sub-circuits of the controller.

Abstract: The present invention discloses an automatic gain controller with an amplifier (10) having an amplifier output connected to a mixer (20) and a receiver signal strength indicator (100) connected to the amplifier output and to a first counter (60). The first counter (60) is adapted to produce a signal to control gain of the amplifier (10) and receives its input from the receiver signal strength indicator (100) which causes the first counter (60) to count up or down depending on the strength of the signal output from the amplifier (10). The automatic gain controller also includes a second counter (70) which is connected to an applications circuit and is adapted to produce a signal to control gain of the mixer (20). The second counter (70) receives its input from a gain control signal from the applications circuit (50) and also from the first counter (60).

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.