Abstract: An operating device of a cross-power domain multiprocessor and a communication method thereof. The device includes: at least two processors, wherein each is connected with a processor channel connected with a memory, and the processor channel includes read and write channels; the memory and an interface parsing unit for controlling the processor channels; the memory includes a shared memory unit and a dedicated memory of each processor; a memory allocation unit for allocating the shared memory and a detection wake-up unit for detecting a processor state and receiving a data transmission command. When the processor with a receiving end in a dormant mode is awoken, information can be saved in the shared memory and processed according to the information priority after the processor is completely awake. The shared memory performs dynamic allocation according to the quantity of the wake-up processors, which improves the communication efficiency between the memory and processors.

Abstract: A FLASH controller includes a main control module; and an arbitration module, a read data fifo, and a write data fifo connected with the main control module. The read data fifo and the write data fifo are both connected with the arbitration module and a data interface module, and the data interface module is connected with an AHB data bus. The controller further includes a register module that is connected with the read data fifo, the write data fifo, the arbitration module, and a configuration interface module. The configuration interface module is connected with an AHB configuration bus, and the main control module is connected with the register module through a synchronization module. The AHB data bus interface and the AHB configuration bus interface are adopted for different operations, and general read-write operations of FLASH are realized through DMA data transfer and high-capacity internal cache units, improving data transfer efficiency.

Abstract: A FLASH controller includes a main control module; and an arbitration module, a read data fifo, and a write data fifo connected with the main control module. The read data fifo and the write data fifo are both connected with the arbitration module and a data interface module, and the data interface module is connected with an AHB data bus. The controller further includes a register module that is connected with the read data fifo, the write data fifo, the arbitration module, and a configuration interface module. The configuration interface module is connected with an AHB configuration bus, and the main control module is connected with the register module through a synchronization module. The AHB data bus interface and the AHB configuration bus interface are adopted for different operations, and general read-write operations of FLASH are realized through DMA data transfer and high-capacity internal cache units, improving data transfer efficiency.

Abstract: A data storage method for speech-related deep neural network (DNN) operations, characterized by comprising the following steps: 1. determining the configuration parameters by a user; 2. configuring a peripheral storage access interface; 3. configuring a multi-transmitting interface of feature storage array; 4. enabling CPU to store to-be-calculated data in a storage space between the feature storage space start address and the feature storage space end address of the peripheral storage device; 5. after data storage, enabling CPU to check the state of the peripheral storage access interface and the multi-transmitting interface of feature storage array; 6. upon receiving a transportation completion signal of the peripheral storage access interface by CPU, enabling the multi-transmitting interface of feature storage array. 7. upon receiving a transportation completion signal of the multi-transmitting interface of feature storage array by CPU, repeating step 6.

Abstract: A data storage method for speech-related deep neural network (DNN) operations, characterized by comprising the following steps: 1. determining the configuration parameters by a user; 2. configuring a peripheral storage access interface; 3. configuring a multi-transmitting interface of feature storage array; 4. enabling CPU to store to-be-calculated data in a storage space between the feature storage space start address and the feature storage space end address of the peripheral storage device; 5. after data storage, enabling CPU to check the state of the peripheral storage access interface and the multi-transmitting interface of feature storage array; 6. upon receiving a transportation completion signal of the peripheral storage access interface by CPU, enabling the multi-transmitting interface of feature storage array. 7. upon receiving a transportation completion signal of the multi-transmitting interface of feature storage array by CPU, repeating step 6.