Abstract: A bus pipeline structure comprises: an n-channel multiplexer at a transmitting end works in an n times of clock domain of a transmitting chiplet; the n-channel multiplexer sends a data flow from the transmitting chiplet to an n-channel de-multiplexer at a receiving end, the n-channel de-multiplexer inputs the received data flow into a first register in an idle state among at least two registers at the receiving end, the first register outputs the received data flow to a receiving chiplet; after a receiving state machine at the receiving end determines that the n-channel de-multiplexer sends the received data flow to the first register, the receiving state machine at the receiving end sends a bus release flag to a transmitting state machine at the transmitting end, and the transmitting state machine receiving the bus release flag controls an n-channel multiplexer to transmit the data flow in a next clock cycle.