Patents Assigned to Chipletz, Inc.
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Patent number: 12660634Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.Type: GrantFiled: May 14, 2025Date of Patent: June 16, 2026Assignee: Chipletz, Inc.Inventors: Michael Su, Michael Alfano, Siddharth Ravichandran
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Patent number: 12568832Abstract: In integrated circuit packages, a coaxial pair of signals are routed through a plated through hole between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods and apparatuses where signals are routed within a concentric reference conductor within traditional package substrates. Methods for forming a hole in the core substrate material through which the coaxial pair of signals is passed on a fine pitch.Type: GrantFiled: June 16, 2025Date of Patent: March 3, 2026Assignee: Chipletz, Inc.Inventors: Bryan Black, Siddharth Ravichandran, Michael Su, Michael Alfano
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Publication number: 20260026360Abstract: Each of a selected plurality of different facilities are fabricated into respective tiles, each tile being fabricated using processes best suited to the function of the facility. After tile testing, a selected set of good tiles is fabricated into a single, monolithic substrate in accordance with a selected layout. After substrate testing, the good substrate is then fabricated into a single advanced package.Type: ApplicationFiled: July 16, 2024Publication date: January 22, 2026Applicant: Chipletz, Inc.Inventors: Siddharth Ravichandran, Michael Su, Michael Alfano, Bryan Black
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Publication number: 20250309082Abstract: In integrated circuit packages, a coaxial pair of signals are routed through a plated through hole between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods and apparatuses where signals are routed within a concentric reference conductor within traditional package substrates. Methods for forming a hole in the core substrate material through which the coaxial pair of signals is passed on a fine pitch.Type: ApplicationFiled: June 16, 2025Publication date: October 2, 2025Applicant: Chipletz, Inc.Inventors: Bryan Black, Siddharth Ravichandran, Michael Su, Michael Alfano
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Publication number: 20250309153Abstract: An advanced semiconductor package substrate with crosstalk mitigation structures and methods of developing the same are provided. More particularly, methods and apparatus in an integrated circuit to mitigate crosstalk between signal traces disposed in a common layout plane of an advanced package are provided. Mitigation structures may be formed by providing at least one reference trace which substantially conforms to the path of that signal trace, essentially following the path of least impedance of the high frequency signal excitation.Type: ApplicationFiled: June 26, 2024Publication date: October 2, 2025Applicant: Chipletz, Inc.Inventors: Ching-Ping Wong, Lawrence Ross, Victor Kronberg
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Publication number: 20250293133Abstract: In integrated circuit packages, a coaxial pair of signals are routed through a plated through hole between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods and apparatuses where signals are routed within a concentric reference conductor within traditional package substrates. Methods for forming a hole in the core substrate material through which the coaxial pair of signals is passed on a fine pitch.Type: ApplicationFiled: June 3, 2025Publication date: September 18, 2025Applicant: Chipletz, Inc.Inventors: Bryan Black, Siddharth Ravichandran, Michael Su, Michael Alfano
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Publication number: 20250273604Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.Type: ApplicationFiled: May 14, 2025Publication date: August 28, 2025Applicant: Chipletz, Inc.Inventors: Michael Su, Michael Alfano, Siddharth Ravichandran
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Publication number: 20250210548Abstract: A fully-integrated voltage regulation module is fabricated into a single, unitary tile. After tile testing, a selected set of good tiles is fabricated into a single, monolithic substrate in accordance with a selected layout. After substrate testing, the good substrate is then fabricated into a single advanced package.Type: ApplicationFiled: November 26, 2024Publication date: June 26, 2025Applicant: Chipletz, Inc.Inventors: Siddharth Ravichandran, Michael Su, Michael Alfano, Bryan Black
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Patent number: 12334455Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.Type: GrantFiled: July 15, 2024Date of Patent: June 17, 2025Assignee: Chipletz, Inc.Inventors: Michael Su, Michael Alfano, Siddharth Ravichandran
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Patent number: 12288756Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.Type: GrantFiled: March 11, 2022Date of Patent: April 29, 2025Assignee: Chipletz, Inc.Inventors: Michael Su, Michael Alfano, Siddharth Ravichandran
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Publication number: 20250015019Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.Type: ApplicationFiled: July 15, 2024Publication date: January 9, 2025Applicant: Chipletz, Inc.Inventors: Michael Su, Michael Alfano, Siddharth Ravichandran
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Publication number: 20240258041Abstract: Structures and methods of forming a thin-film electrolytic capacitor without the conductive polymer, thus improving the ESR performance as well as the reliability of the capacitor. Thin-film electrolytic capacitor structures include sintered anode, oxide deposition, conductive polymer, conductive metal inks, and metal cathodes.Type: ApplicationFiled: January 31, 2024Publication date: August 1, 2024Applicant: Chipletz, Inc.Inventors: Siddharth Ravichandran, Michael Alfano, Bryan Black, Michael Su
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Publication number: 20240120293Abstract: A semiconductor package substrate with embedded crack cessation structures and methods of forming the same is provided. Crack cessation structures include blind vias structures, through vias structures, and methods of forming the same are provided. Crack cessation structures may be formed by trenching of one or more structures, and deposition of metallic or insulative materials to form a crack cessation structures in the semiconductor package substrate core.Type: ApplicationFiled: October 10, 2023Publication date: April 11, 2024Applicant: Chipletz, Inc.Inventors: Michael Su, Siddharth Ravichandran, Michael Alfano, Bryan Black
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Publication number: 20230395305Abstract: A semiconductor package substrate with embedded passive devices and methods of forming the same is provided. Embedded passive devices include inductors and inductor modules and methods of forming the same are provided. Embedded inductors may be formed by deposition of magnetic core material, trenching of one or more channels, and placement of conductive wires to form an module embeddable in the semiconductor package substrate core. Provided are methods and apparatus for formation of embeddable pot-core, toroidal, and helical inductors.Type: ApplicationFiled: June 7, 2023Publication date: December 7, 2023Applicant: Chipletz, Inc.Inventors: Siddharth Ravichandran, Michael Su, Michael Alfano, Bryan Black
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Publication number: 20230343687Abstract: In integrated circuit packages, a coaxial pair of signals are routed through a plated through hole between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods and apparatuses where signals are routed within a concentric reference conductor within traditional package substrates. Methods for forming a hole in the core substrate material through which the coaxial pair of signals is passed on a fine pitch.Type: ApplicationFiled: April 22, 2023Publication date: October 26, 2023Applicant: Chipletz, Inc.Inventors: Bryan Black, Siddharth Ravichandran, Michael Su, Michael Alfano
