Abstract: The present invention provides a method for preparing a dielectric layer on a surface of a wafer, a wafer structure, and a method for shaping a bump. The preparation method includes: providing a wafer; forming an alignment mark on the wafer, the thickness of the alignment mark being not less than 0.3 ?m; and forming a dielectric layer on the wafer where the alignment mark is formed. In the present application, before the dielectric layer is shaped on a surface of the wafer, the alignment mark is prepared in advance on the surface of the wafer, thereby avoiding the need of reworking due to an invisible alignment mark in a preparation stage of the dielectric layer, and ensuring the continuity of the process.

Abstract: The present invention discloses a method for packaging a chip-on-film (COF). The method includes: S1, forming a plurality of first pins on a circuit surface of a flexible circuit substrate, and forming a plurality of second pins on a chip to be packaged; S2, arranging to keep the circuit surface always facing downwards, arranging to keep a surface of the chip to be packaged, where the second pins matching the first pins are arranged, always facing upwards, and arranging the first pins and the second pins, to be opposite to each other; and S3, applying a top-down pressure to the flexible circuit substrate, and/or applying a bottom-up pressure to the chip to be packaged, and simultaneously heating at high temperature to solder the first pins and the second pins in a fused eutectic manner. The method of the present invention improves the product yield and stability.

Abstract: The present invention discloses a wafer rewiring double verification structure, and a manufacturing method and a verification method thereof, wherein the wafer rewiring double verification structure includes: a die having a substrate, a plurality of pads and a passivation layer; a plurality of rewiring modules; and a gap portion formed between every two adjacent rewiring modules. A dielectric module is disposed on each rewiring module, and is provided with an inclined surface; and an electroplated layer is disposed on the inclined surface. According to the present invention, functional verification can be performed on different rewiring modules on the same wafer in one manufacturing process.

Abstract: The present invention provides a chip packaging structure and a chip packaging method. The chip packaging structure includes a substrate, a metal bonding pad disposed on the substrate and a metal wire, wherein the tail end of the metal wire is provided with a welding part, the welding part is welded to the metal bonding pad, the metal bonding pad is provided with a coating layer, and at least part of the welding part is located between the coating layer and the metal bonding pad. The present invention greatly improves a welding effect of the metal wire and the metal bonding pad, so that the welding of the metal wire and the metal bonding pad is more reliable and stable.