Abstract: A chip structure including a substrate, a plurality of chip bonding pads and a plurality of test-bonding-pad sets is provided. The substrate has an active surface and the chip bonding pads are disposed on the active surface. At least part of the chip bonding pads is arranged along a first line. The test-bonding-pad sets are disposed on the active surface and arranged along a second line, wherein the first line is parallel to the second line and the pitches between neighboring test-bonding-pad sets are the same. Each test-bonding-pad set has a plurality of test bonding pads. The test bonding pads are electrically connected to the chip bonding pads arranged along the first line. The distances between the test bonding pads of each test-bonding-pad set and the first line are different. Accordingly, there is no increase in the cost for electrical testing said chip structure.