Patents Assigned to Chips and Technologies, LLC.
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Patent number: 6553153Abstract: A method and apparatus for reducing video data. The apparatus is composed of a plurality of reducers. A block is received, corresponding to a plurality of color space components and having a width defined by a plurality of pixels digitally represented by bytes. The video data is first reduced by performing power of two reduction. This is followed by fine scale reduction to achieve the final reduced image.Type: GrantFiled: December 3, 1998Date of Patent: April 22, 2003Assignee: Chips and Technologies, LLC.Inventor: Ying Cui
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Patent number: 6211859Abstract: A method for displaying grey-scale images at a desired grey scale resolution up to the visible limit on a display having a matrix of pixels, includes the steps of: defining a plurality of control matrices, each of said control matrices having a size and equal to the desired grey scale resolution of the display, each position in each of said control matrices corresponding to a specific pixel of said display; defining a super matrix, each position in said super matrix corresponding to one of said plurality of control matrices and having an assigned number in a range equal to the desired grey scale resolution; turning on a selected number of pixels within each of said control matrices based upon the grey scale value of the pixel, the orientation of the pixels turned on based on the value of a circular queue of size equal to said desired gray scale resolution; and adjusting the starting value of said circular queue for each of said control matrices based upon the number contained in the position of the super matrType: GrantFiled: February 24, 1998Date of Patent: April 3, 2001Assignee: Chips & Technologies, LLCInventors: Jian Lin, Shih-hua Chang, Carrell R. Killebrew, Jr.
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Patent number: 6205181Abstract: A method and apparatus for storing a macroblock from a video data stream is disclosed. A macroblock is received, the macroblock having a plurality of blocks corresponding to a plurality of color space components and having a width defined by a plurality of pixels. According to a first aspect of the present invention, the macroblock is stored in a vertical strip format. According to a second aspect of the present invention, the contents of the plurality of blocks are interleaved. According to a third aspect of the present invention, the contents of the plurality of blocks are interleaved and the macroblock is then stored in a vertical strip format.Type: GrantFiled: March 10, 1998Date of Patent: March 20, 2001Assignee: Chips & Technologies, LLCInventors: Xiaoping Hu, Hungviet H. Nguyen, David Sokmin Kang
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Patent number: 6125412Abstract: A system for performing input and output operations to and from a processor in which interrupts for I/O operations are conditionally generated internally rather than externally by (Super State.TM.) microcode residing in a separate address space in memory in an area protected from the user. A (superblock) register in the processor points to the Super State area in memory. If the Super State mode is turned on, an interrupt is generated within the processor whenever the control table allows. The interrupt directs the processor to the register and hence to the Super State code. By way of example, the Super State code controls power and access to the port, decides whether to put the interrupt in memory and emulate the I/O, and counts access to the port. The invention provides a processor with the flexibility of performing I/O operations to and from memory and/or to a peripheral or to trap an interrupt into a new operating environment for device emulation.Type: GrantFiled: April 9, 1993Date of Patent: September 26, 2000Assignee: Chips & Technologies, LLCInventors: James A. Picard, Morris E. Jones, Jr.
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Patent number: 6034663Abstract: A method for displaying grey-scale images at a desired grey scale resolution on a display having a matrix of pixels, comprises the steps of: defining a control matrix having a size smaller than the entire display and equal to the desired grey scale resolution of the display, each position in the control matrix having an address assigned such that unintended artifacts in the display are controlled; horizontally and vertically mapping the control matrix into the display such that each pixel in the matrix of pixels in the display corresponds to an address in a control matrix mapped into the display; comparing control matrix address of each pixel in a frame of an image to be displayed on the display to a range of address values and turning that pixel on if the grey scale value of that pixel is within the range of address values, the range of address values arranged in a circular queue and being equal to the grey scale value of that pixel; and shifting the range of address values in the circular queue for successiType: GrantFiled: March 10, 1997Date of Patent: March 7, 2000Assignee: Chips & Technologies, LLCInventors: Carrell R. Killebrew, Jr., Jian Lin, Shih-hua Chang
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Patent number: RE37069Abstract: The present invention relates to An apparatus for converting cathode ray tube (CRT) data to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame four panel refresh frames. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.Type: GrantFiled: August 29, 1995Date of Patent: February 27, 2001Assignee: Chips & Technologies, LLCInventors: Ignatius B. Tjandrasuwita, James E. Margeson, III