Abstract: A design of logic circuitry to be tested is divided into one or more discrete logic modules usable in other designs of circuitry. An automated test pattern generator (ATPG) program and its tools are applied to the discrete module while not also being applied to the remainder of the logic circuitry, with the result that an ATPG pattern is provided for the module. When the module is reused in another design of logic circuitry, the ATPG pattern is also reusable in such other design.

Abstract: A method of generating a graphical image, such as a font, is described in which expansion data for an image portion that is not to be written is never added to source data for such portion.

Abstract: A circuit suitable for use in electronic systems which utilize Synchronous Dynamic Random Access Memory (SDRAM), and method according to the present invention comprises an application-specific integrated circuit. When a burst command is initiated by the memory controller, causing the SDRAM to perform a data transfer into or out of memory which require many consecutive clock cycles to complete, the circuit recognizes the SDRAM commands as those commands appear on the instruction bus. The circuit then analyzes other operations which are pending and which might be performed during otherwise unusable time periods while the burst operation is being performed by the SDRAM. The circuit issues instructions to initiate and complete these operations prior to the SDRAM command being completed.

Abstract: A text image stretching system in a VGA for a plurality of text image font sizes comprises a plurality of cell line replication registers having inputs and outputs, the plurality of cell line replication registers formed into groups corresponding to one of the plurality of text image font sizes, each cell line replication register having a plurality of bits, the inputs of the plurality of cell line replication registers connected to the VGA to receive cell line replication information for storage in the plurality of cell line replication registers, a multiplexer having data inputs, first and second select inputs and a plurality of outputs, each of the data inputs connected to one of the plurality of bits of the plurality of cell line replication registers, the first and second select inputs decoded to select one bit from each of the cell line replication registers in one of the groups of the cell line replication registers to form a cell line replication code for output on the plurality of outputs, a repeat c

Abstract: A switch array decoding circuit, suitable for use in a keyboard, and method according to the present invention comprises a matrix of row lines and column lines. Switches from the array are connected between intersections of the row lines and column lines. The row lines and column lines are connected to I/O pins leading to one or more components containing the decoder circuitry. The decoder circuitry first simultaneously drives the row lines while sensing the column lines. When a switch closure is detected, the states of all column lines are simultaneously sensed. This operation determines the column position(s) of the one or more switches being closed. The column lines are then simultaneously driven while simultaneously sensing the row lines. This operation determines the row position(s) of the one or more switches being closed. The row and column drive and sense order may be reversed.

Abstract: In a video controller system including a video memory and first and second pluralities of functional circuits which access the video memory, requests for access to the video memory among more than one of the functional circuits are arbitrated by two levels of arbitration. In the first level of arbitration, a buffer in each of said first pluralities of functional circuits temporarily stores data read from or to be written to the video memory. A priority is assigned to requests for access from each of the functional circuits. A low limit and a high limit are assigned for each of the buffers. Requests for access to the video memory from all of the functional circuits are monitored. Each of the buffers is monitored to indicate whether the amount of data in each buffer is below the low limit or above the high limit. Access to the video memory is granted first to any requesting ones of the functional circuits whose buffers are below the low limit in order of the assigned priority.

Abstract: The invention pertains to the adaptive vertical stretching of an original image so that the resulting stretched image optimally fits within the vertical boundary of a display having a fixed number of pixel lines. A line replication state machine provides the stretching of the original image, while a line replication generator preferably generates new line replication numbers by sequentially incrementing an initial line replication number in an integer by integer fashion. A display image measuring device provides a display fit status to the state machine, enabling the state machine to determine whether a resulting stretched image fits within the display exceeded the vertical height of the display. The state machine toggles between two types of line stretching that gives a stretched image closely fitted to the maximum image size available in an applicable display.

Abstract: A ring oscillator is embedded into the same silicon wafer as the functional circuits. The output of the ring oscillator and a display clock signal are both directed into seperate inputs of a multiplexer which is controlled by the computer BIOS. When the BIOS desires to read the ring oscillator frequency, the multiplexer is switched, thus providing the output of the ring oscillator to the display status register. The resulting frequency may be used to optimize clock speeds.

Abstract: Two methods and apparatus for reducing power consumption in battery powered computers are disclosed. The first places the computer in a sleep mode whenever a certain data input function is called. The second applies statistical analysis to calls to another data input function. By measuring the number of times the computer has tried to read data from the keyboard over the past predefined period, the variance between the high and low number of calls over the present and preceding time periods, and whether the number of times the computer has tried to read data has both exceeded the present limit and remained within the preset variance limit for a predefined minimum time, the desirability of activating a sleep mode for the computer can be determined.

Abstract: A cache controller with both burst and hidden refresh modes. In the burst mode, refresh requests are counted, but not acted on, until a predetermined number of refresh requests have been received. At that time, multiple refreshes are done in a single sequence. Although the amount of time taken for actually refreshing the memory is the same, the time needed for arbitration to obtain control of the necessary busses is reduced, giving an overall savings of time. In the hidden refresh mode, a refresh is done, but no hold signal is sent back to stop the CPU while the refresh is being done. Circuitry is provided which allows local memory accesses, but holds other memory accesses until the refresh is completed. Thus, local memory accesses, which expect data quickly, are not inhibited and other memory accesses, which the CPU expects may take some time, can be held up without the CPU knowing.

Abstract: A method and apparatus for performing a fast jump address calculation is disclosed. A field from the instruction is provided to an adder, on the assumption that it is the displacement value, without actually determining whether it is a displacement value. A fixed instruction length is also provided to the adder, on the assumption that the instruction will have that length. Finally, the current instruction address bits from the program counter are provided to the adder. These are added together to provide a jump address.

Abstract: A printed circuit board design capable of accepting both first and second versions of an IC device. First and second IC devices (10, 20) have pins disposed along respective first and second rectangular peripheries (12a-b and 15a-b; 22a-b and 23a-b). Each pin on the first IC device has a functional counterpart pin on the second IC device. The board configuration contains pads in first and second arrays (32a-b and 35a-b; 32a, 32c, 33a-b) that correspond to the pins on the first and second IC devices. At least some of the pads (32b) of the first array do not physically coincide with pads in the second array and are located within the rectangle defined by the second array. Each non-overlapping pad in the first array is connected by a circuit board trace (40) to a respective pad in the second array such that each circuit board trace joins two pads corresponding to counterpart pins.

Abstract: A system for masking bits in a configuration. The system has a bus with first and second sets of bit lines. A line from the first set is paired with aline from the second set; the paried lines are coupled to each cell in the configuration register. A logic circuit is connected to each register cell and the corresponding paired lines. Depending upon the state of the bit signal of the second set bit line, the logic circuit passes the bit signal on the first set bit line for loading into the register cell or reloads the bit line signal already in the register cell. In this manner, masking operations in the configuration register can be performed very quickly.

Abstract: An improved memory controller which can support varying numbers of banks of memory without requiring any more RAS output pins than are necessary for a minimum number of banks of memory. The memory controller chip has N RAS output pins. An internal decoder selects one of N decode outputs after decoding internally provided coded RAS addresses. A timing signal is generated to control the duration of the selected decoder output to provide the proper pulse length for the RAS signal. An internal multiplexer, with its outputs coupled to the RAS output pins, selects either the N decode outputs from the decoder or the timing signal and the internally provided addresses directly.

Abstract: The present invention provides a memory addressing system that can accommodate multiple size DRAMS. DRAMS of various sizes can be mixed in a variety of ways. The present invention provides a hardware register associated with each pair of banks of DRAMS. This hardware register is programmable to indicate the type of DRAMS that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks. Using this technique, it is not necessary to insert the largest memory chips in the first memory bank. Memory chips of either size can be inserted in either set of memory banks and the information in the programmable register is used to control circuitry which appropriately modifies the accessing signals which are sent to the memory system.