Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Abstract: A method of forming a polymer support ring, or collar, around the base of solder balls used to form solder joints includes forming patterned regions of uncured polymer material over each of the conductive solder bump pads on an IC package or other substrate to which the solder balls are to be attached. Preferably, the uncured polymer material is a no-flow underfill material that fluxes the solder bump pads. Pre-formed solder balls are then placed into the uncured polymer material onto their respective solder bump pads. A subsequent heating cycle raises the assembly to the reflow temperature of the solder balls, thereby attaching the solder balls to the underlying solder bump pads, and at least partially curing the polymer material to form a support collar at the base region of each attached solder ball.

Abstract: A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Abstract: A method and an apparatus for reading a given digital pulse signal of variable length in the domain of a first clock frequency and creating a pulse output signal that is synchronized in the domain of a second clock. The number of cycles the input pulse signal is active, in terms of the first clock, is the same number of cycles as the resulting output signal is active, where for the output signal the number of cycles is measured by the second clock.