Abstract: A method of Atomic Force Microscopy (AFM). A first drive signal is generated for causing a periodic motion of a probe tip in a direction normal to a sample surface. The first drive signal has a known amplitude and frequency. A bias signal is generated for applying an electric potential to the probe tip relative to a potential the sample surface. At least one component of the bias signal is oscillatory and correlated with the periodic motion of the probe tip. A response of the probe tip is detected, and analyzed by a processor to infer information about a composition of the sample surface.

Abstract: A system is disclosed for displaying circuitry interconnections as flightlines between a component specified as the local component and the foreign components connecting to the local component. Upon obtaining data of the circuit components and interconnections, a user can designate the local component from among all of the circuit components. The system determines the foreign components connected to that local component, retrieves the flightline appearance display settings for the computer display, and renders a view of the specified local component and its foreign components with flightlines representing each interconnection connection. The flightlines can be color coded to indicate inputs, outputs or other characteristics of interest to the user.

Abstract: Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry cells. The system groups together cells that feed into the same combination of one or more state cells. The groups of cells are then replaced by clouds which are defined in the netlist for the sequential digital circuitry to produce a simpler representation of the circuitry for analysis purposes and to aid in determining the function of those cells for which the function is unknown.

Abstract: Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry cells. The system groups together cells that feed into the same combination of one or more state cells. The groups of cells are then replaced by clouds which are defined in the netlist for the sequential digital circuitry to produce a simpler representation of the circuitry for analysis purposes and to aid in determining the function of those cells for which the function is unknown.

Abstract: A system is disclosed for displaying circuitry interconnections as flightlines between a component specified as the local component and the foreign components connecting to the local component. Upon obtaining data of the circuit components and interconnections, a user can designate the local component from among all of the circuit components. The system determines the foreign components connected to that local component, retrieves the flightline appearance display settings for the computer display, and renders a view of the specified local component and its foreign components with flightlines representing each interconnection connection. The flightlines can be color coded to indicate inputs, outputs or other characteristics of interest to the user.

Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.

Abstract: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene circuits. This provides high contrast images that permits circuit layout extraction software to readily distinguish between metal lines and vias.

Abstract: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene circuits. This provides high contrast images that permits circuit layout extraction software to readily distinguish between metal lines and vias.

Abstract: A system and method for aligning tile images of an area of interest of an integrated circuit having N metal layers M, where N>1, includes a parametric representation algorithm for extracting parametric representations of edges from an image showing metal layer (MN) and at least a proportion of metal layer (MN?1) of the integrated circuit to produce a parametric representation of the edges visible on the respective metal layers. The parametric representations include an indication of the metal layer with which each extracted edge is associated and at least one of x and y coordinates associated with each of the extracted edges.

Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.

Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.

Abstract: A three-dimensional model of a semiconductor chip is produced from coarsely aligned mosaic images of respective layers of the semiconductor chip using an improved method for aligning the mosaic images, so that minimal operator intervention is required to produce the model. A line detection algorithm is applied to each of the mosaic images to produce a set of line segments identified by x and y coordinates of end points of the line segments with respect to a frame defined by a mosaic image in which each line segment occurs. Virtual reference marks are established using end points of different mosaic images that are vertically aligned to within an uncertainty of the coarse alignment of the mosaic images, and the virtual reference marks are used to compute a mean adjustment of the x and y coordinates of each of the mosaic images to produce a three dimensional coordinate space.

Abstract: A method of recalibrating to compensate for thermal drift between a micro-imaging system and a sample integrated circuit (IC) under investigation determines a planar drift using a cross-correlation between a reference calibration image and a recalibration image, and further determines a focus drift from a difference between a reference focus setting and a recalibration focus setting. The recalibration is performed on detection of a recalibration trigger event, such as expiry of a recalibration time interval. The recalibration time interval can be adaptively adjusted based on a magnitude of the thermal drift. Tile images captured since a last recalibration are recaptured if the thermal drift is too great for reliable image compensation. The system ensures seamless assembly of tile images into image photo-mosaics and increases image photo mosaic throughput.

Abstract: A mesh is created from selected focus points having locations on a surface of interest of a sample being micro-imaged. The mesh and associated focus settings of the focus points are used to define adjacent focus facets forming a focus surface substantially coincident with the surface of interest of the sample. In micro-imaging the sample, a micro-imaged portion of the surface of interest is segmented for the purpose of acquiring tile images. A tile image focus location is used to extract a tile image focus setting from the focus surface. A tile image focus determination process selects a focus facet coincident with the tile image focus location and interpolates a tile image focus setting from focus settings associated with the focus points defining the focus facet. If a coincident focus facet is not found, the tile image focus setting is set to the focus setting of a nearest focus point. Dependence on autofocus is thus eliminated, providing faster imaging and better focused images.

Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.

Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.

Abstract: Methods of caching tile image constituents of image-mosaics enable a substantially smooth real-time display of portions of the image-mosaic in a view during panning, resizing, or zooming of the view. The method includes using a predictive algorithm to identify tile images to be retrieved from a remote store through a local area network, and for sequencing requests for the retrieval of tile images from the remote store. A scheduler calculates time spent in retrieving and servicing each tile image retrieval request and proportionately pauses retrieval of tile images after each request is serviced in order to prevent over utilizing LAN resources. The advantages are that tile images to be displayed are cached in accordance with a priority to facilitate image display while network data transfers are distributed in time.

Abstract: An apparatus for extracting design and layout information from image-mosaics of a progressive deconstruction of a semiconductor integrated circuit (IC) includes a visual display, a system pointer and a plurality of lockstep cursors. The visual display displays views of an area of interest of the respective image-mosaics. Each view displays one of the lock-step cursors when appropriate, as determined by a position of the system pointer. When the system pointer is within a view, a corresponding lock-step cursor is displayed as a master-cursor, while other views display a lock-step cursor that has a different size and shape than the master-cursor. All lock-step cursors move in unison under the control of the master-cursor. A method for extracting design and layout information from image-mosaics uses the lock-step cursors to quickly match features across image-mosaics, and to avoid transposition errors while tracing features from one image-mosaic to another.

Abstract: A method of imaging an integrated circuit using a focused ion beam system is presented. According to the method an integrated circuit is imaged in plan-view using a focused ion beam system. Circuit information is then extracted absent processing. In another embodiment, a method and system for imaging an entire IC automatically without removing the IC from the imaging system and requiring minimal operator intervention is presented. The method employs a focused ion beam system to image an exposed layer of an integrated circuit and then to etch a portion of the exposed layer in situ. Imaging and etching are repeated until substantially the entire integrated circuit is imaged. A processor is used to assemble the layers into a three-dimensional topography of the integrated circuit. Because of known relationships between layers, the mosaicing is facilitated and the final topography is more reliable than those produced by currently known computer implemented methods.

Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.