Patents Assigned to Chipworks Inc.
  • Patent number: 8495556
    Abstract: A system is disclosed for displaying circuitry interconnections as flightlines between a component specified as the local component and the foreign components connecting to the local component. Upon obtaining data of the circuit components and interconnections, a user can designate the local component from among all of the circuit components. The system determines the foreign components connected to that local component, retrieves the flightline appearance display settings for the computer display, and renders a view of the specified local component and its foreign components with flightlines representing each interconnection connection. The flightlines can be color coded to indicate inputs, outputs or other characteristics of interest to the user.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: July 23, 2013
    Assignee: Chipworks Inc.
    Inventor: Michael Green
  • Patent number: 8413085
    Abstract: Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry cells. The system groups together cells that feed into the same combination of one or more state cells. The groups of cells are then replaced by clouds which are defined in the netlist for the sequential digital circuitry to produce a simpler representation of the circuitry for analysis purposes and to aid in determining the function of those cells for which the function is unknown.
    Type: Grant
    Filed: April 9, 2011
    Date of Patent: April 2, 2013
    Assignee: Chipworks Inc.
    Inventor: Michael Green
  • Patent number: 7509601
    Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 24, 2009
    Assignee: Chipworks Inc.
    Inventors: David F. Skoll, Terry Ludlow, Julia Elvidge
  • Patent number: 7498181
    Abstract: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene circuits. This provides high contrast images that permits circuit layout extraction software to readily distinguish between metal lines and vias.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: March 3, 2009
    Assignee: Chipworks Inc.
    Inventors: Lev Klibanov, Sherri Lynn Griffin
  • Publication number: 20070072314
    Abstract: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene circuits. This provides high contrast images that permits circuit layout extraction software to readily distinguish between metal lines and vias.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: CHIPWORKS INC.
    Inventors: Lev Klibanov, Sherri Lynn Griffin
  • Publication number: 20070031027
    Abstract: A system and method for aligning tile images of an area of interest of an integrated circuit having N metal layers M, where N>1, includes a parametric representation algorithm for extracting parametric representations of edges from an image showing metal layer (MN) and at least a proportion of metal layer (MN?1) of the integrated circuit to produce a parametric representation of the edges visible on the respective metal layers. The parametric representations include an indication of the metal layer with which each extracted edge is associated and at least one of x and y coordinates associated with each of the extracted edges.
    Type: Application
    Filed: August 4, 2005
    Publication date: February 8, 2007
    Applicant: CHIPWORKS INC.
    Inventors: Neal Stansby, Lev Klibanov
  • Publication number: 20050226521
    Abstract: A three-dimensional model of a semiconductor chip is produced from coarsely aligned mosaic images of respective layers of the semiconductor chip using an improved method for aligning the mosaic images, so that minimal operator intervention is required to produce the model. A line detection algorithm is applied to each of the mosaic images to produce a set of line segments identified by x and y coordinates of end points of the line segments with respect to a frame defined by a mosaic image in which each line segment occurs. Virtual reference marks are established using end points of different mosaic images that are vertically aligned to within an uncertainty of the coarse alignment of the mosaic images, and the virtual reference marks are used to compute a mean adjustment of the x and y coordinates of each of the mosaic images to produce a three dimensional coordinate space.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Applicant: Chipworks Inc.
    Inventors: Alexander LaChance, Zygo Blaxell